Pipelined interpretive digital data processor comprised of a mul

Details Pipelined interpretive digital data processor comprised of a mul Pipelined interpretive digital data processor comprised of a mul

1979-03-23

1982-08-24

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 900, G06F 700

Patent

active

043464351

ABSTRACT:
A pipelined interpretive-type digital data processing system supporting one or more input high level languages is comprised of a multi-level hierarchy of processors designatable in descending order as S, M, N and P processors and operable so that the processor at each level interprets instructions at the level above in a pipelined manner. Each of the S, M and N processors is provided with its own memory for respectively storing S, M and N instructions which are selected and fetched during system operation so as to provide a hierarchical interpretation of each input high level language. This is accomplished in a manner such that fetched M instructions are first processed by the N-processor in accordance with corresponding fetched N instructions before being employed by the M-processor for processing data.

REFERENCES:
patent: 3805247 (1974-04-01), Zucker
patent: 3970993 (1976-07-01), Finnila
patent: 3983539 (1976-09-01), Faber et al.
patent: 4131941 (1978-12-01), Siegel

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