Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Reducing an impact of a stall or pipeline bubble
Reexamination Certificate
2005-08-16
2005-08-16
Kim, Kenneth S. (Department: 2111)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Reducing an impact of a stall or pipeline bubble
C712S208000, C713S322000, C718S107000
Reexamination Certificate
active
06931516
ABSTRACT:
A pipelined instruction decoder for a multithread processor including an instruction decode pipeline, a valid bit pipeline, and a thread identification pipeline in parallel together, with each having the same predetermined number of pipe stages. The instruction decode pipeline to decode instructions associated with a plurality of instruction threads. The valid bit pipeline to associate a valid indicator at each pipe stage with each instruction being decoded in the instruction decode pipeline. The thread identification pipeline to associate a thread-identification at each pipestage with each instruction being decoded in the instruction decode pipeline. The pipelined instruction decoder may further include a pipeline controller to control the clocking of each pipe stage of the instruction decode pipeline, the valid bit pipeline, and the thread identification pipeline. The pipeline controller may invalidate an entire thread of instructions, squeeze out invalid instructions, and/or conserve power by selectively stopping the clocking of pipestages.
REFERENCES:
patent: 5357617 (1994-10-01), Davis et al.
patent: 5778246 (1998-07-01), Brennan
patent: 5890008 (1999-03-01), Panwar et al.
patent: 5913049 (1999-06-01), Shiell et al.
patent: 5983339 (1999-11-01), Klim
patent: 6026476 (2000-02-01), Rosen
patent: 6357016 (2002-03-01), Rodgers et al.
patent: 6385719 (2002-05-01), Derrick et al.
patent: 6594755 (2003-07-01), Nuechterlein et al.
patent: 6754808 (2004-06-01), Roth et al.
patent: WO93/01545 (1992-07-01), None
Eugene R. Hnatek; Random-Access Memories and Content-Addressable Memories, A User's Handbook of Semiconductor Memories; 19971 pp. 591-608; Wiley-Interscience Pub.
William Stallings;7.3 Memory Management, computer Organization and Architecture, Designing for Performance, 4th Edition; 1996; pp. 240-263; Prentice Hall NJ.
Hamcher, Veranesic & Zaky; The Main Memory, Computer ORganization, 2nd Edition; 1984; pp. 306-329; McGraw-Hill Book Company.
Patterson & Hennessy; Memory-Hierachy Design, Computer Architecture: A Quantitative Approach; 1990 pp. 408-475; Morgan Kaufmann Pub.; San Mateo, CA.
Richard Kain; Advanced Computer Architecture: A Systems Design Approach; 1996; pp. 75-88 and 456-474; Prentice Hall, Englewood Cliffs, NJ.
Jean-Loup Baer; computer Systems Architecture; 1980 pp. 139-166 and 315-325; Computer Sceince Press; Rockville, MD.
Deleganes Daniel J.
Douglas Jonathan P.
Hadley James D.
Blakely Sokoloff Taylor and Zafman
Intel Corporation
Kim Kenneth S.
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