Pipelined dual port integrated circuit memory

Details Pipelined dual port integrated circuit memory Pipelined dual port integrated circuit memory

1997-07-29

1998-07-14

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Simultaneous operations

36518921, 36523005, 365233, 365239, 365154, G11C 1604

Patent

active

057814805

ABSTRACT:
A pipelined dual port integrated circuit memory (20) includes an array (30) of static random access memory (SRAM) cells, where each of the memory cells (80) is connected to a single word line (72) and to a single bit line pair (74, 76). A control circuit (32) controls access to the memory cells, where substantially simultaneous requests for access are serviced sequentially within a single cycle of a clock signal of a data processor that is accessing the memory (20). An address collision detector (110) compares addresses provided to the two ports, and generates a match signal that is used for determining which of the two ports are serviced first, independent of which port is read from, or written to. Because dual port functionality is obtained using a single port SRAM array (30), the memory (20) may be manufactured using relatively less integrated circuit surface area, and therefore at a lower cost.

REFERENCES:
patent: 5036491 (1991-07-01), Yamaguchi
patent: 5341341 (1994-08-01), Fukuzo
patent: 5375089 (1994-12-01), Lo
Motorola, Inc., Motorola Semiconductor Technical Data, "Advance Information 64K .times.18 Bit Synchronous Dual I/O, Dual Address SRAM", #MCM69D618/D, pp. 1-16.
Motorola, Inc., Motorola Fast SRAM Data, "Fast Static RAM Component and Module Data", #MCM62110, pp. 4-10 -4-41.
Motorola Semiconductor Technical Data, "Advance Information 64K .times.18 Bit Synchronous Separate I/O Fast SRAM", #MCM69Q618/D, 12 pgs.
Quality Semiconductor, Inc., "QS70261A, QS70261A, Preliminary, High-Speed CMOS 16K .times.16 Asynchronous Dual-Port RAM", MDSF-00012-06, Jun. 6, 1996, pp. 1-22.

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