Pipelined dual port integrated circuit memory

Details Pipelined dual port integrated circuit memory Pipelined dual port integrated circuit memory

1998-06-23

2000-06-20

Nguyen, Viet Q.

Static information storage and retrieval

Read/write circuit

Simultaneous operations

36518901, 36518905, 36518908, 36523008, 365233, G11C 700

Patent

active

060785276

ABSTRACT:
A pipelined dual port integrated circuit memory (20) includes an array (21) of static random access memory (SRAM) cells, wherein each of the memory cells (80) is connected to a single word line (72) and to a single bit line pair (74, 76). Each port's access is performed synchronously with respect to a corresponding clock signal. The two clock signal signals are asynchronous with respect to each other. When access requests are received from both ports substantially simultaneously, an arbitration circuit (24) determines which port receives priority. The port which receives priority accesses the array (21) first. The arbitration circuit (24) ensures that substantially simultaneous access requests are serviced sequentially and occur within a single cycle of a corresponding clock signal.

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