Pipelined data relocation and improved chip architectures

Details Pipelined data relocation and improved chip architectures Pipelined data relocation and improved chip architectures

2004-05-13

2009-02-10

Lamarre, Guy J (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

Reexamination Certificate

active

07490283

ABSTRACT:
The present invention present methods and architectures for the pipelining of read operation with write operations. In particular, methods are presented for pipelining data relocation operations that allow for the checking and correction of data in the controller prior to its being re-written, but diminish or eliminate the additional time penalty this would normally incur. A number of architectural improvements are described to facilitate these methods, including: introducing two registers on the memory where each is independently accessible by the controller; allowing a first memory register to be written from while a second register is written to; introducing two registers on the memory where the contents of the registers can be swapped.

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