Pipelined cyclic redundancy check for high bandwidth interfaces

Details Pipelined cyclic redundancy check for high bandwidth interfaces Pipelined cyclic redundancy check for high bandwidth interfaces

2011-03-08

2011-03-08

Alphonse, Fritz (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S763000, C714S781000

Reexamination Certificate

active

07904787

ABSTRACT:
Techniques for validating the integrity of a data communications link are provided. By executing error correction/detection calculations, such as CRC calculations, in a pipelined manner, logic may be distributed over multiple machine cycles. As a result, delay involved in the logic for each cycle may be reduced, allowing calculations in systems with higher clock frequencies.

REFERENCES:
patent: 5111458 (1992-05-01), Hara
patent: 5303302 (1994-04-01), Burrows
patent: 6411984 (2002-06-01), Leach et al.
patent: 6530057 (2003-03-01), Kimmitt

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