Pipelined clock stretching circuitry and method for I2C...

Details Pipelined clock stretching circuitry and method for I2C... Pipelined clock stretching circuitry and method for I2C...

2008-02-29

2010-10-19

Lee, Thomas (Department: 2116)

Electrical computers and digital processing systems: support

Clock control of data processing system, component, or data...

Reexamination Certificate

active

07818604

ABSTRACT:
A system for increasing the data throughput of an I2C bus including a serial clock conductor (3) for conducting a serial clock signal (SCK) and a serial data conductor (2) for conducting a serial data signal (SDA) includes clock-stretching control circuitry (15) coupled to the serial clock conductor (3) for stretching the serial clock signal (SCK) by holding the serial clock conductor (3) at a predetermined level to cause a master device (10) to stop sending the serial clock signal, and circuitry (FIG.3) in the slave device (5) for releasing stretching of the serial clock signal (SCK) in response to a determination by the slave device (5) that stretching of the serial clock signal (SCK) is unnecessary.

REFERENCES:
patent: 5925135 (1999-07-01), Trieu et al.
patent: 6502202 (2002-12-01), Song
patent: 6874047 (2005-03-01), Duguay et al.
patent: 2005/0114567 (2005-05-01), Lambrache et al.
The I2C-Bus Specification, Version 2.1, Philips Semiconductors, Jan. 2000, pp. 1-46.

Affiliated with

Also associated with

Rating

Pipelined clock stretching circuitry and method for I2C... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Pipelined clock stretching circuitry and method for I2C..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Pipelined clock stretching circuitry and method for I2C... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4218998