Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
2006-11-28
2006-11-28
Trujillo, James K. (Department: 2116)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C713S500000, C713S400000, C713S401000, C345S506000, C345S029000
Reexamination Certificate
active
07143302
ABSTRACT:
A pipeline structure is provided for use in a digital system. The pipeline structure includes stages arranged in a sequence from a first stage for receiving an input of the pipeline structure to a last stage for providing an output of the pipeline structure. At least one intermediate stage is interposed between the first stage and the last stage. The pipeline structure also includes a phase shifting circuit for generating at least one local clock signal for controlling the at least one intermediate stage. The first stage and the last stage are controlled by a main clock signal, the at least one local clock signal is generated from the main clock signal, and the main clock signal and the at least one local clock signal are out of phase. Also provided is a method of operating a pipeline structure that includes stages arranged in a sequence.
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Pappalardo Francesco
Pennisi Agatino
Bongini Stephen
Fleit Kain Gibbons Gutman Bongini & Bianco P.L.
Jorgenson Lisa K.
STMicroelectronics S.r.l.
Sugent James F.
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