Pipeline stage single cycle sliding alignment correction of...

Details Pipeline stage single cycle sliding alignment correction of... Pipeline stage single cycle sliding alignment correction of...

2005-05-03

2005-05-03

Kim, Hong (Department: 2186)

Electrical computers and digital processing systems: processing

Instruction alignment

C712S219000, C712S300000, C714S045000, C714S017000, C703S026000, C713S401000, C713S503000, C711S201000

Reexamination Certificate

active

06889311

ABSTRACT:
Trace data is aligned in a processor having an instruction pipeline by delaying write data and read data a predetermined number of clock cycles, selectively swapping both most significant write data and read data with least significant write data and read dependent upon memory access control data. The write and read data pass normally for even memory bank accesses and are swapped for odd memory bank accesses. Memory access control data, program counter data and program counter control data are similarly delayed. At least the read data and optionally all the data are held upon a pipeline stall.

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