Pipeline replay support for unaligned memory operations

Details Pipeline replay support for unaligned memory operations Pipeline replay support for unaligned memory operations

2006-11-07

2006-11-07

Treat, William M. (Department: 2181)

Electrical computers and digital processing systems: processing

Instruction alignment

C712S024000, C712S225000, C711S201000

Reexamination Certificate

active

07134001

ABSTRACT:
Instructions asserted in a microprocessors instruction pipeline (3) are accompanied by control information, comprising a group of bits, asserted within a control information pipeline (5) that is synchronized to the instruction pipeline. At the execution stage, the control information is interpreted and appropriate action taken. The control information may indicate that the instruction has been reasserted (asserted again following an initial assertion) and may also indicate the number of times that the instruction has been consecutively asserted in the instruction pipeline. Applied to unaligned memory operations, in which a memory atom is asserted twice, the control information indicates which part of the unaligned data is to be fetched each time the atom is executed.

REFERENCES:
patent: 5325495 (1994-06-01), McLellan
patent: 5778423 (1998-07-01), Sites et al.
patent: 6112297 (2000-08-01), Ray et al.

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