Electrical computers and digital processing systems: processing – Instruction alignment
Reexamination Certificate
1999-10-20
2004-04-27
Treat, William M. (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction alignment
C712S023000, C712S024000, C712S218000, C712S222000, C711S201000
Reexamination Certificate
active
06728865
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to digital computers, and, more particularly, to a novel method and apparatus for reducing complexity of the logic circuits required to handle unaligned memory operations.
BACKGROUND
The operation of a digital computer is controlled by computer programs, such as operating systems and application programs. Those programs provide instructions to those functional units of a central processor in the digital computer responsible for handling and execution as binary information. Different binary sequences represent different instructions for a particular machine and the instructions tend to be unique to a particular processor or processor family. Thus, typically, different families of processors have different instruction sets, unless they are specifically designed to utilize an instruction set of another processor family.
The instructions of one processor typically cannot be understood directly by any of the other types of processors. The difference in instruction sets is often due to the format chosen by the designer for presenting instructions to the processor. In general, a designer may chose to design a processor for a complex instruction set computer (CISC) or reduced instruction set computer (RISC) or for a newer very long instruction set (VLIW) computer.
CISC processors provide special hardware for executing an entire operation. For example, an ADD instruction may provide one operand to an integer unit register, fetch a second operand from memory and place it in a second register, and combine the two operands in a third register. Because it does so, instruction formats are very complicated. Such structure takes a large amount of hardware and processing effort to tell one instruction from another. A RISC processor, on the other hand, is much simpler and treats each part of an ADD operation as a separate element. By providing consistently sized instructions, a RISC processor eliminates significant hardware and reduces the processing time needed to decode instructions.
A newer type of processor called a very long instruction word (VLIW) processor attempts to make use of the best attributes of both CISC and RISC. It uses consistent sized instructions (herein called “atoms”) as do RISC processors, but groups a number of those instructions together in a VLIW word (herein called a “molecule”) and provides processing units to execute the individual atoms in parallel.
The execution of most operations by a processor requires a number of steps. For example, instructions must be fetched from memory, sometimes a second instruction must be fetched from memory, the instruction is decoded and finally it is executed. This takes a number of operational cycles of the processor. In order to produce results as fast as possible, computers are designed so that each sequential instruction is begun (as far as is possible) on the next operation cycle after the preceding instruction has already begun the steps leading to its execution. This causes the steps leading to execution of subsequent instructions to overlap. In this manner, an instruction may often be executed each cycle.
The manner in which this starting and carrying out the steps leading to the execution of instructions so that an instruction executes each operation cycle is referred to by those skilled in the art as an instruction pipeline, which is included within processors. In operation to process an application program, the instructions of the application are serially entered into the pipeline by a pipeline control unit. The pipeline control unit includes a program counter, that loads instructions in a serial order into the pipeline. Via that pipeline, instructions are presented to a respective functional execution unit of the processor that is to execute the instruction.
Instructions do not always execute in the ideal order provided by the pipeline. Often things happen which interfere with the process. For example, a memory page at which an instruction resides may not be in main memory and must be paged in before the instruction can execute. Exceptions occur for a wide variety of reasons. When such exception occurs, further internal processing activity of the application program is temporarily halted, until that exception is resolved. The excepting functional unit issues a stop signal, herein called a “kill” signal, which pauses all other functional units in the microprocessor, until the exception is resolved, empties the pipeline of any instructions and immediately prompts an exception handler into action.
The exception handler fixes the problem which has arisen. An exception handler is a software routine conventionally designed to deal with such exceptions; and different exception handlers exist to handle each different kind of exceptions. A different routine is prepared to handle different exception. Thus, every computer contains a library of such software handlers in its associated memory. The pipeline control unit calls up an appropriate exception handler and executes that routine.
As an example, if a memory exception is due to the failure to locate data referenced by a load instruction within main memory, the exception handler is one that pages in that data and then returns back to the original excepted instruction. Processing of the application recommences with re-execution of the same instruction. However, this time the instruction is executed without generating that memory exception. In rare instances an exception handler of a RISC or CISC processors may emulate the instruction that caused the exception and then execute the emulated instruction to achieve the result desired. In other instances, an exception handler may only note that an exception occurred and return control to the excepted instruction or may decide to skip the excepted instruction and have execution resume at the next instruction. The exception handler thereafter returns control to the instruction pipeline controller by issuing a “return-from-exception” (RFE) signal. The latter signals the pipeline counter in the pipeline control unit to reissue and execute the instruction that was subject to the exception or, alternatively as called for by the exception handler, signals to advance the next instruction into the pipeline, that is, insert the memory address of the succeeding instruction into the pipeline, thereby moving pipeline activity beyond the instruction that generated the exception. In either event, the return-from-exception procedure is a very simple step.
Such a simple step of skipping past an excepted instruction is not possible for VLIW processors. In VLIW processors it is frequently desired for exception handlers to emulate an excepting atom instruction. Although re-execution of the excepting atom instruction is not desired, other atoms in the same molecule instruction must be executed. For example, one VLIW computer system is described U.S. Pat. No. 5,832,205 to Kelly et al, granted Nov. 3, 1998, entitled, Memory Controller For A Microprocessor For Detecting A Failure of Speculation On The Physical Nature of A Component Being Addressed (the '205 Kelly patent), assigned to Transmeta Corporation, assignee of the present invention, the content of which is incorporated by reference herein in its entirety. The present invention has particular application to VLIW computers, and, in particular, to VLIW computers described by the '205 Kelly patent, although it should be understood that the invention may be found to also be applicable to other types of computers.
The '205 Kelly patent discloses a novel microprocessor formed by a combination of a hardware processing portion, much simpler in structure than competitive prior state of the art microprocessors, and an emulating software portion, referred to therein as “code morphing software”. Among other things, in the Kelly system the code morphing software carries out a significant portion of the functions of processors in software, thereby reducing the hardware required for processing and the greater electrical power that such hardware requir
Coon Brett
D'Souza Godfrey
Serris Paul
Transmeta Corporation
Treat William M.
LandOfFree
Pipeline replay support for unaligned memory operations does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Pipeline replay support for unaligned memory operations, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Pipeline replay support for unaligned memory operations will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3235143