Pipeline processing device and interrupt processing method

Details Pipeline processing device and interrupt processing method Pipeline processing device and interrupt processing method

2007-10-09

2007-10-09

Sparks, Donald (Department: 2181)

Electrical computers and digital processing systems: processing

Processing control

C712S220000, C712S214000, C712S211000

Reexamination Certificate

active

10854146

ABSTRACT:
At an MA stage, data, such as a header address of an interrupt processing routine, is loaded via a data bus and immediately supplied to a program counter via multiplexers without the intervention of an instruction decode stage in accordance with a setting address outputted from an EXE/MA buffer to an address bus. Thus, at the next processing timing at which the header address of the interrupt processing routine is loaded, the loaded header address is set in the program counter and fetching of a header instruction of the interrupt processing routine so that the interrupt processing routine can be immediately started.

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