Pipeline module circuit structure with reduced power...

Details Pipeline module circuit structure with reduced power... Pipeline module circuit structure with reduced power...

2006-05-09

2006-05-09

Browne, Lynne H. (Department: 2116)

Electrical computers and digital processing systems: support

Clock control of data processing system, component, or data...

C713S322000, C713S330000

Reexamination Certificate

active

07043658

ABSTRACT:
A pipeline module circuit structure with reduced power consumption and a method for operating the pipeline module circuit structure are provided. The pipeline module circuit structure comprises a plurality of pipeline stages and a clock generator, each of the pipeline stages connected to adjacent pipeline stages through a bus. A clock controller is installed in each of the pipeline stages, so as to set the clock frequency of a preceding pipeline stage to an idle frequency or stop when a present pipeline stage starts to operate and to set the clock frequency of a next pipeline stage to an operation frequency when the present pipeline stage is about to cease, such that the power consumption of the pipeline module circuit structure is effectively reduced.

REFERENCES:
patent: 5740087 (1998-04-01), Smentek et al.
patent: 6611920 (2003-08-01), Fletcher et al.
patent: 2002/0175839 (2002-11-01), Frey

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