Pipeline microprocessor with conditional jump in one clock...

Details Pipeline microprocessor with conditional jump in one clock... Pipeline microprocessor with conditional jump in one clock...

2000-05-03

2004-01-13

Ellis, Richard L. (Department: 2183)

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

Reducing an impact of a stall or pipeline bubble

C712S233000

Reexamination Certificate

active

06678819

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a pipeline microprocessor comprising a program counter, a circuit for the incrementation of the program counter, means to decode a set of instructions of the microprocessor comprising means to decode a conditional jump instruction of the program counter and a computation unit comprising a first output to deliver a result and a second output to deliver status bits of the result.
The present invention also relates to the execution of a conditional jump instruction in a pipeline microprocessor of the above type.
The term “conditional jump instruction” refers in the present application to a jump instruction JMPc from the program counter PC of a microprocessor whose execution depends on the result of a previous instruction. For example, the following instructions are conditional jumps:
1) JMPc IF C=0 VAL (jump with a value VAL if C=0),
2) JMPc IF N=0 VAL (jump with a value VAL if N=0),
3) JMPc IF P=0 VAL (jump with a value VAL if P=0),
4) JMPc IF Z=0 VAL (jump with a value VAL if Z=0),
the bit C (“carry”) being the sum carry bit (or overflow bit), the bit N being the sign bit, the bit P being the parity bit and the bit Z being the zero value bit of the result of an operation performed by an arithmetic and logic computation unit ALU. These bits C, N, P, Z or flags are conventionally stored in a register called Rf (“flags register”).
In the prior art, a conditional jump instruction cannot be executed before the result of the previous instruction is known and before the register Rf containing the flags is updated. This necessity contradicts the fact that, in a pipeline microprocessor, the steps of processing two successive instructions overlap one another with a shift of one rank. By way of example, we shall consider the following program sequence:
(1) (ADR
1
) SUB R
1
,R
2
,R
3
(2) (ADR
2
) JMPC IF Z=1 VAL,
which means:
(1) “subtract the contents of a register R
3
from the contents of a register R
2
and record the result in a register R
3
”,
(2) “jump program to address ADR
2
+VAL if the result is zero, else go to immediately following address ADR
3
of the program”,
and implies the processing steps described here below, each step being performed in one clock cycle:
1.1—reading of the instruction SUB at the address ADR
1
of the program memory of the microprocessor, and incrementation of the program counter PC (ADR
1
becomes ADR
2
),
1.2—decoding of the instruction SUB,
1.3—reading of the registers R
2
and R
3
,
1.4—subtraction by the unit ALU of the contents of the register R
3
from the contents of the register R
2
,
1.5—recording of the result of the subtraction in the register R
1
and recording in the register Rf of the flags C, N, P, Z delivered by the unit ALU,
2.1—reading of the instruction JMPc at the address ADR
2
and normal incrementation of the program counter (ADR
2
becomes ADR
3
),
2.2—decoding of the instruction JMPc,
2.3—reading of the flag z in the register Rf; if Z=1, computation of the address ADR
2
+VAL and loading of this address in the program counter PC.
In a pipeline processing chain, the steps 1.x and 2.x here above should be processed simultaneously with a one-rank shift. However, it can be seen that the step 2.3 cannot overlap the step 1.4 because the result of the previous operation is not yet available in the register Rf. Also, a new instruction following the instruction JMPc cannot be read before the step 2.3 of the instruction JMPc has ended because it is not yet known at what address this instruction has to be read.
Thus, the standard approach to overcome this drawback consists in suspending the injection of a new instruction into the pipeline chain until the flags C, N, P, Z are loaded into the register Rf (step 1.5) and the conditional jump instruction is processed (step 2.3).
This method has the drawback of temporarily blocking the working of the pipeline chain and slowing down the performance of a program. Generally, the time lost for the execution of a program is proportional to the number of conditional jumps that the program contains.
The main goal of the present invention is to provide for a pipeline microprocessor structure for the execution of a conditional leap instruction without interruption of the pipeline processing chain.
The document U.S. Pat. No. 5,349,671, with reference to its FIGS. 1 to 4, describes a microprocessor comprising four pipeline stages, respectively for the reading of an instruction, the decoding of the instruction, the execution of the instruction and the storage of the result, as well as means for the decoding [
3
a
,
3
b
] and execution [
6
a
,
6
b
] of a conditional jump instruction. T he decoding means [
3
a
,
3
b
] are connected both to the state register [
2
] of the microprocessor and to the output of the computation unit ALU [
4
] which delivers the flags of the microprocessor. More particularly, these decoding means comprise a first circuit [
3
a
] for the evaluation of a call address, connected to the state register [
2
], a second circuit [
3
b
] for the evaluation of a call address, connected to the above-mentioned output of the unit ALU and a flag-updating detector whose output indicates whether or not the instruction being executed is capable of modifying the flags of the microprocessor. When a conditional jump instruction is decoded, the choice of the read address of the following instruction is entrusted is entrusted to the first [
3
a
] or second [
3
b
] evaluation circuit according to the indication given by the flag-updating detector.
SUMMARY OF THE INVENTION
The present invention seeks an alternative to this conventional pipeline microprocessor structure and is aimed especially at providing means for the decoding and processing of a conditional jump instruction that is simpler than those described here above.
A secondary goal of the present invention is to provide a pipeline microprocessor structure that is simple and consumes little current.
To attain these goals, the present invention provides for a microprocessor of the type mentioned here above in which the computation unit and the means for decoding the conditional jump instruction are laid out in two neighboring pipeline stages, and the means for decoding the conditional jump instruction are connected to the second output of the computation unit.
According to one embodiment, the microprocessor comprises a first pipeline stage and a second pipeline stage, each comprising a first sector and a second sector, the first sector of each stage being active during a first clock half-cycle and the second sector of each stage being active during a second clock half-cycle.
According to one embodiment, the means of decoding the conditional jump instruction are laid out in the first sector of the first pipeline stage and the computation unit is laid out in a first sector of the second pipeline stage.
According to one embodiment, the means for decoding the conditional jump instruction are laid out in the second sector of the first pipeline stage and the computation unit is laid out in the first sector of the second pipeline stage.
According to one embodiment, the incrementation circuit of the program counter is laid out in the second sector of the first pipeline stage.
Advantageously, the microprocessor has a bank of registers belonging in read mode to the first sector and in write mode to the second sector of the second pipeline stage. This characteristic makes it possible to simplify the structure of the microprocessor which may have only two pipeline stages, providing for greater efficiency in electrical consumption, and the execution of compact instructions comprising only one operational code, the address of a source register and the address of a destination register of the result of the operation designated by the instruction.
According to one embodiment, the sectors of the second pipeline stage are demarc

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