Pipeline circuit for low latency memory

Details Pipeline circuit for low latency memory Pipeline circuit for low latency memory

2007-07-10

2007-07-10

Choi, Woo H. (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S138000, C711S140000

Reexamination Certificate

active

10461295

ABSTRACT:
The embodiments herein describe a memory device and method for reading and writing data. In one embodiment, a memory device is provided comprising a memory array and first and second data buffers in communication with the memory array. The second data buffer comprises a larger storage capacity than the first data buffer. During a write operation, data is stored in the second data buffer and then stored in the memory array. During a read operation, data is read from the memory array and then stored in the first data buffer but not in the second data buffer. Because the smaller-storage-capacity buffer takes less time to fill than the larger-storage-capacity buffer, there is less of a delay in outputting data from the memory device as compared to memory devices that use a larger-storage-capacity buffer for both read and write operations. Other embodiments are provided, and each of the embodiments can be used alone or in combination with one another.

REFERENCES:
patent: 6034882 (2000-03-01), Johnson et al.
patent: 6420215 (2002-07-01), Knall et al.
patent: 6525953 (2003-02-01), Johnson
patent: 6563745 (2003-05-01), Ilkbahar
patent: 6567287 (2003-05-01), Scheuerlein
patent: 6574145 (2003-06-01), Kleveland et al.
patent: 2002/0028541 (2002-03-01), Lee et al.
patent: 2003/0043643 (2003-03-01), Scheuerlein et al.
patent: 2003/0070044 (2003-04-01), Jeddeloh
patent: 2003/0081489 (2003-05-01), Scheuerlein et al.
patent: 2003/0097535 (2003-05-01), Hsu et al.
patent: 2003/0115514 (2003-06-01), Ilkbahar et al.
patent: 2003/0185048 (2003-10-01), Fricke et al.
patent: 2004/0077204 (2004-04-01), Zeng
patent: 2005/0076152 (2005-04-01), Huppenthal et al.
“A Compact On-Chip ECC for Low Cost Flash Memories”, IEEE Journal of Solid State Circuits, vol. 32, No. 5, May 1997.
“FAM 17.8: A 1Mb CMOS DRAM with Fast Page and Static Column Modes”, ISSCC 85 Friday 15, 1985/East Ballroom/12:15 p.m. Session XVII: Megabit DRAMs.
“FAM 19.8: A 1Mb DRAM with 33 MHz Serial I/O Ports”, ISSCC 86/ Friday, Feb. 21, 1986/Pacific Ballroom/ 12:15 p.m. Session XIX: Dynamic RAMs.
“Flash Memory Data Book”, Silicon Storage Technology, Inc. 1996.
“Partial Selection of Passive Element Memory Cell Sub-Arrays for Write Operation”, Roy E. Scheuerlein and Matthew P. Crowley, U.S. Appl. No. 09/748,649, filed Dec. 22, 2000.
“Three-Dimensional Memory”, Monty Cleeves, U.S. Appl. No. 10/185,508, filed Jun. 27, 2002.
“High Density 3D Rail Stack Arrays and Method of Making”, Kedar Patel, Alper Ilkbahar, Roy Scheuerlein and Andrew J. Walker, U.S. Appl. No. 10/180,046, filed Jun. 27, 2002.
“An Improved Method for Making High-Density Nonvolatile Memory”, S. Brad Herner, Maitreyee Mahajani and Michael A. Vyvoda, U.S. Appl. No. 10/326,470, filed Dec. 19, 2002.
“Semiconductor Device with Localized Charge Storage Dielectric and Method of Making Same”, Alper Ilkabahar, Roy Scheuerlein, Andrew Walker and Luca Fasoli, U.S. Appl. No. 10/325,951, filed Dec. 23, 2002.
“Programmable Memory Array Structure Incorporating Series-Connected Transistor Strings and Methods for Fabrication and Operation of Same”, Roy E. Schererlein, Christopher Petti, Andrew J. Walker, En-Hsing Chen, Sucheta Nallamothu, Alper Ilkbahar, Luca Fasoli, Igor Kouznetsov, U.S. Appl. No. 10/335,078, filed Dec. 31, 2002.
“Method for Fabricating Programmable Memory Array Structures Incorporating Series-Connected Transistor Strings”, Andrew J. Walker, En-Hsing Chen, Sucheta Nallamothu, Roy E. Scheuerlein, Alper Ilkbahar, Luca Fasoli, Igor Kouznetsov, Christopher Petti, U.S. Appl. No. 10/335,089, filed Dec. 31, 2002.

Affiliated with

Also associated with

Rating

Pipeline circuit for low latency memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Pipeline circuit for low latency memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Pipeline circuit for low latency memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3732187