Pipe latch circuit for increasing data output speed, a...

Details Pipe latch circuit for increasing data output speed, a... Pipe latch circuit for increasing data output speed, a...

2006-07-18

2008-09-02

Auduong, Gene N (Department: 2827)

Static information storage and retrieval

Read/write circuit

Sipo/piso

C365S189050, C365S233100

Reexamination Certificate

active

07420865

ABSTRACT:
A pipe latch circuit for increasing data output speed, a semiconductor memory device with the pipe latch circuit and data output operation method of the same. The pipe latch circuit includes a selection signal generator and a pipe latch unit. The selection signal generator generates input selection signals in response to an input control signal and a first selection control signal. The pipe latch unit inverts pre-fetch data received in parallel through a plurality of GIO (Global Input and Output) lines into serial pipe output data in response to input selection signals, a second selection control signal and output control signals and then outputs them at an output node. The pipe latch unit includes an input selection unit for selectively changing a parallel order of pre-fetch data respectively received through a plurality of GIO lines in response to an input selection signals and then respectively outputting input selection data at a plurality of internal data lines in accordance with the change result. The pipe latch circuit has the advantage of increasing data output speed by reducing an output path of pre-fetch data delivered at GIO lines and thus reducing the change of voltage level of the pre-fetch data.

REFERENCES:
patent: 5488730 (1996-01-01), Brown et al.
patent: 6687185 (2004-02-01), Keeth et al.
patent: 6762974 (2004-07-01), Johnson et al.
patent: 1020010004202 (2001-01-01), None
patent: 1020040043843 (2004-05-01), None
patent: 1020040059983 (2004-07-01), None
Notice of Allowance for Korean appl. 10-2006-0026098.

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