Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-01-15
2003-05-20
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S291000
Reexamination Certificate
active
06566697
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a novel pinned photodiode pixel architecture and method of using the pixel for high-speed motion-capture CMOS image sensors. In particular, the invention relates to a pinned photodiode used in a five-transistor pixel so that the channel region of the photodiode is completely voided of charge after reset and readout operations.
2. Description of Related Art
CMOS image sensors first came to the fore in relatively low-performance applications where shuttering was not required, scene dynamic range was low, and moderate to high noise levels could be tolerated. Pixels were based on simple diode architectures, and the pixel circuits were based on the minimum gate count required for bussing and buffering (usually 3). Although these early sensors offered a route to low total system costs (integration of all camera functionality on a single chip) and low power dissipation, the pixel architectures did not allow for low reset noise, snapshot image capture, and antiblooming/exposure control. As the art progressed, pixels were developed with four transistors and with pinned photodiode (PPD) photosites. These advancements allowed for shuttered operation with low reset noise. However, they did not allow antiblooming or exposure control. In U.S. patent application Ser. No. 09/722,609, titled “Five Transistor CMOS Pixel”, incorporated herein by reference, a photosite is disclosed that could be realized with either a conventional photodiode or with a PPD in which an additional transistor allows for snapshot operation with antiblooming and exposure control.
FIGS. 2A and 2B
are circuit schematics of conventional CMOS pixels known as a 3T pixel (for three-transistor pixel) and a 4T pixel (for four-transistor pixel). The 3T pixel has a reverse-biased photodiode coupled between substrate voltage VSUB and the reset gate transistor. When operated, an RST signal applied to the electrode of the reset gate transistor causes a reverse bias equal to output drain voltage VOD less VT to be set on the photodiode. Between drain supply VDD and output signal terminal OUT are coupled two series transistors. The drain of the first transistor is coupled directly to VDD, and a gate of the first transistor is coupled to the cathode of the photodiode so that the first transistor operates as a source follower. The source of the source follower transistor is coupled through a row transistor to output terminal OUT. In applications, a plurality of such 3T pixels are coupled to the same output terminal OUT. By selectively applying row address signal ROW to the gate of the selected row transistor, different pixels can be coupled to output terminal OUT.
The 4T pixel (
FIG. 2B
) is like the 3T pixel (
FIG. 2A
) except that the 4T pixel has a transfer gate transistor coupled between the reset transistor and the photodiode so that a sense node may be created between the transfer gate transistor and the reset transistor. The sense node may be isolated from the photosite.
There is a need to capture fast-changing scenes without the intrusion of a “rolling shutter” artifact while at the same time allowing for antiblooming and/or exposure control functionality. Further, there is a need to operate the pixel without image lag and with minimal fixed pattern noise due to variations in the fat zero signal. Known cameras use external shutters, mechanical or otherwise, to eliminate the rolling shutter artifacts.
U.S. Pat. No. 5,900,623 to Tsang et al. describes a five transistor pixel with two transistors arranged as a differential pair. However, operation of the Tsang et al. pixel requires that complementary signals be applied to FETs in a differential configuration, and that photocharge be accumulated on capacitor MCAP at a drain of one of the differentially configured FETs. The Tsang et al. pixel does not allow for electronically “shuttered” image acquisition. Further, Tsang et al does not describe a 5T pixel using a pinned photodiode so that the channel region of the photodiode is completely voided of charge after reset and readout operations.
U.S. Pat. No. 6,115,065 to Yadid-Pecht and Fossum describes a pixel with four transistors and a photogate in a configuration of a 4T pixel. This pixel does not provide protection against a rolling shutter artifact (as described herein) at the same time as antiblooming and exposure control. Further, Yadid-Pecht and Fossum does not describe a 5T pixel using a pinned photodiode so that the channel region of the photodiode is completely voided of charge after reset and readout operations.
U.S. Pat. No. 6,002,123 to Suzuki describes a 4T pixel. However, the pixel does not provided antiblooming functionality at the same time as it provides protection against the rolling shutter artifact. Further, Suzuki does not describe a 5T pixel using a pinned photodiode so that the channel region of the photodiode is completely voided of charge after reset and readout operations.
U.S. Pat. No. 5,760,723 to McGrath et al. describes a CCD spill well architecture that makes use of a fill and spill methodology. Further, McGrath et al. does not describe a 5T pixel using a pinned photodiode so that the channel region of the photodiode is completely voided of charge after reset and readout operations.
SUMMARY OF THE INVENTION
It is an object to the present invention to provide a pixel compatible with CMOS processing technology. It is another object of the present invention to provide a pixel that can be voided of photo charges.
These and other objects are achieved in a pixel that includes five transistors, a pinned photodiode and a storage node. A first transistor is coupled between the surface pinned photodiode and the storage node. A second transistor is coupled between the storage node and an output drain voltage. A third transistor is coupled between the pinned photodiode and a pixel reset voltage.
In an alternative embodiment, the pixel reset voltage is different than the output drain voltage.
These and other objects are also achieved by a method of sensing radiation in a pixel. The method includes steps of applying an exposure control clock signal to a gate electrode of an exposure control transistor of a five-transistor pixel, applying a pixel preset voltage to a drain of the exposure control transistor, and switching the exposure control clock signal to a low state at a beginning of an integration cycle.
These and other objects are also achieved by a method that includes steps of draining all charge from a pinned photodiode in a five transistor pixel into a preset drain before a beginning of an integration cycle and isolating the pinned photodiode at the beginning of the integration cycle. The method also includes a step of transferring all charge from the pinned photodiode into a storage node at an end of the integration cycle.
These and other objects are also achieved by a method of using a five transistor pixel. The method includes steps of draining all of a prior charge from a pinned photodiode through an exposure control gate transistor of the five transistor pixel and integrating a first charge on the pinned photodiode during an integration fraction of a first readout interval.
These and other objects are also achieved by another method of using a five transistor pixel. The method includes steps of integrating a first charge on a pinned photodiode of the five transistor pixel during an integration fraction of a first readout interval and transferring all of the first charge from the pinned photodiode to a storage node at an end of the first readout interval.
These and other objects are also achieved by a sensor that includes control circuitry and a pixel that includes five transistors, a pinned photodiode and a storage node. In the sensor, a first transistor is coupled between the pinned photodiode and the storage node. Additionally, a second transistor is coupled between the storage node and an output drain voltage. Further, a third transistor is coupled between the pinned photodiode and a pixel reset drain. The control
Fox Eric C.
O Nixon
Dalsa Inc.
Dorsey & Whitney LLP
Ngo Ngan V.
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