Pin reordering during placement of circuit designs

Details Pin reordering during placement of circuit designs Pin reordering during placement of circuit designs

2006-06-06

2006-06-06

Lin, Sun James (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07058915

ABSTRACT:
A method (400) of placing a circuit design can include the steps of identifying topological levels of a circuit design representation (415) and determining an arrival time for each input signal to a look up table within a circuit design representation (420). The propagation delay associated with each pin of the look up table can be identified (420) such that the input signals of the look up table can be ordered according to the arrival times of each input signal and the propagation delay of each pin of the look up table (435). The method can continue processing each look up table of an identified topological level (440) as well as each topological level of the circuit design representation (455).

REFERENCES:
patent: 5461576 (1995-10-01), Tsay et al.
patent: 5729468 (1998-03-01), Cox
patent: 5850355 (1998-12-01), Molnar
patent: 5956257 (1999-09-01), Ginetti et al.
patent: 6591407 (2003-07-01), Kaufman et al.
“Bus Deskewing Method using a Self-Adjusting Variable Delay Element”, IBM Technical Disclosure Bulletin, Oct. 1994, vol. 37, iss. 10, pp. 499-500.
Tsing-Fa Lee et al.; “An effective Methodology for Function Pipelining”; 1992 International Conference on Computer Aided Design; Nov. 8-12, 1992; Copyright IEEE 1992; pp. 230233.

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