Pin management of accelerator for interpretive environments

Details Pin management of accelerator for interpretive environments Pin management of accelerator for interpretive environments

1997-02-13

1999-11-09

Cabeca, John W.

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

Virtual machine memory addressing

711163, 711167, 711123, 709102, 709103, 709301, 710 8, G06F 0932

Patent

active

059833106

ABSTRACT:
An apparatus and method for accelerating interpreters, interpretive environments, may manage pinning of a processor cache closest to a processor. An instruction set implementing a virtual machine may store each instruction in a single cache line as a compiled, linked loaded image. After loading, the cache is pinned, disabled from flushing the contents or replacing the contents of any cache line. A fast load may flush the cache and run an application containing the entire virtual machine instruction set. A pin manager may be hooked into a scheduler in a multi-tasking operating system to load, pin, and unpin the processor cache as rapidly as needed. Thus, the processor cache may be available for general use, except when pinned for use by a virtual machine, such as an interpretive environment. Level-1 caches integrated into central processing units, particularly instruction caches or code caches are ideally suited to implementation of the invention.

REFERENCES:
patent: 5249286 (1993-09-01), Alpert et al.
patent: 5301312 (1994-04-01), Christopher, Jr. et al.
patent: 5369749 (1994-11-01), Baker et al.
patent: 5394547 (1995-02-01), Correnti et al.
patent: 5414848 (1995-05-01), Sandage et al.
patent: 5459867 (1995-10-01), Adams et al.
patent: 5471591 (1995-11-01), Edmonson et al.
patent: 5553305 (1996-09-01), Gregor et al.
patent: 5555398 (1996-09-01), Raman
patent: 5651136 (1997-07-01), Denton et al.
patent: 5745762 (1998-04-01), Celi, Jr. et al.
patent: 5778226 (1998-07-01), Adams et al.
patent: 5781792 (1998-07-01), Asghar et al.
Andrew S. Tanenbaum, "Structured Computer Organization", Prentice-Hall, Inc., pp. 10-12, 1984.

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