Pin grid array package

Details Pin grid array package Pin grid array package

1990-08-21

1991-09-03

Picard, Leo P.

Electricity: conductors and insulators

Boxes and housings

Hermetic sealed envelope type

357 74, H01L 2302

Patent

active

050456393

ABSTRACT:
A pin grid array package having a substrate formed from a ceramics containing a 90% or higher alumina composition. The substrate has an palladium-silver layer on an upper surface thereof with a silver layer further provided on the Pd-Ag layer and a gold bonding pad on a outer periphery of a cavity of the substrate so as to provide electrical connection between pins and chip. The Ag layer is covered with a dielectric layer to prevent contamination from moisture.

REFERENCES:
patent: 4072816 (1978-02-01), Gedney et al.
patent: 4458291 (1984-07-01), Yanagisawa et al.
patent: 4823234 (1989-04-01), Konishi et al.
patent: 4861944 (1989-08-01), Jones, II et al.
patent: 4941582 (1990-07-01), Morikawa et al.

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