Pilot transistor for quasi-vertical DMOS device

Details Pilot transistor for quasi-vertical DMOS device Pilot transistor for quasi-vertical DMOS device

1995-06-07

1997-11-04

Brown, Peter Toby

Active solid-state devices (e.g., transistors, solid-state diode

Test or calibration structure

257329, 257335, 257337, 257341, 257343, H01L 2978, H01L 2702

Patent

active

056843054

ABSTRACT:
An isolated pilot transistor 100 for a QVDMOS device 10 has a gate and drain region in symmetry with the sources 20 of device 10 and an additional resistance 116 in the drain 118 to compensate for current spreading between the source 120 and the buried layer resistor 132.

REFERENCES:
patent: 4313126 (1982-01-01), Krumm et al.
patent: 4554512 (1985-11-01), Aiello
patent: 5256893 (1993-10-01), Yasuoka
patent: 5387875 (1995-02-01), Tateno
patent: 5442216 (1995-08-01), Gough
Weyers et al., A 50 V Smart Power Process with Dielectric Isolation by 51 MOX, IEDM 92-225-228, IEEE.
European Search Report mailed Sep. 12, 1996.for EP 96 40 0695.
PCT Communication mailed Oct. 15, 1996 for PCT/US96/08826.
A. Watson Swager, "Power ICs Weighing The Benefits Of Integration", EDN-Electrical Design News, vol. 39, No. 14, Newton, MA, Jul. 1994, pp. 68-72, 74, 76, 78, 80, 82.

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