Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-10-05
2001-03-20
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S330000, C257S332000, C257S347000
Reexamination Certificate
active
06204532
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
This invention generally relates to the field of semiconductor processing and integrated circuit manufacturing. More specifically, the present invention relates to vertical scaling of semiconductor devices.
2. Background Art
Today, our society is heavily dependent on high-tech electronic devices for everyday activity. Integrated circuits are the components that give life to our electronic devices. Integrated circuits are found in widespread use throughout the world, in appliances, in televisions and personal computers, and even in automobiles. Additionally, modern manufacturing and production facilities are becoming increasingly dependent on the use of machines controlled by integrated circuits for operational and production efficiencies. Indeed, in many ways, our everyday life could not function as it does without integrated circuits. These integrated circuits are manufactured in huge quantities throughout the world. Improved integrated circuit manufacturing processes have led to drastic price reductions and performance enhancements for these devices.
The traditional integrated circuit fabrication process is a series of steps by which a geometric pattern or set of geometric patterns is transformed into an operational integrated circuit. An integrated circuit consists of superimposed layers of conducting, insulating, and device-forming materials. By arranging predetermined geometric shapes in each of these layers, an integrated circuit that performs the desired function may be constructed. The overall fabrication process consists of the patterning of a particular sequence of successive layers.
Integrated circuits are chemically and physically integrated into a substrate material, such as a silicon or gallium arsenide wafer, by combining electrically conductive, semi-conductive, and insulating (dielectric) layers or regions. The layers and regions are arranged to form electronic components or devices such as transistors, diodes, and capacitors. Millions of these devices are formed essentially simultaneously on the surface of a single wafer of semiconductor material during processing.
For example, in a typical fabrication process, a layer of aluminum or some other metal is deposited on the surface of the wafer substrate. The metal layer is patterned to form interconnect paths along the surface of the wafer substrate. The substrate typically contains certain dopant materials which form transistor components. Examples of possible substrate components include N-wells or P-wells, sources, drains, and junctions. In most processes, an insulating or dielectric layer is then deposited over the first metal layer. Vias, or holes, are then created in the dielectric layer and a second metal layer is deposited over the dielectric layer. The second metal layer covers the intervening dielectric layer and fills the via openings in the dielectric layer down to the first metal layer. These filled via openings provide electrical connections between the first and second metal layers. The second metal layer is also patterned to form additional circuit devices and paths. The dielectric layer acts as an insulator between the first and second metal layer. This process can be repeated with additional layers as necessary to create the desired functionality in the circuits located on the wafer.
As the art of semiconductor fabrication has progressed, horizontal scaling has become an increasingly important concern. Specifically, the current emphasis in most fabrication processes is the effort to increase device density by shrinking the amount of real estate each individual device or component occupies on the surface of the wafer. In order to minimize package and device sizes, and maximize device yield for a given wafer size, the goal is to pack as may circuit elements as possible in a given square centimeter of surface area. While great advances in horizontal scaling have been realized, there are certain physical limitations which currently impede additional reductions.
One of the most significant problems experienced as devices get smaller is channel length reduction. Since the width of the gate conductor defines the channel length, as the width of the gate conductor decreases, the channel length also decreases. Due to well known fabrication process variations, the channel length will vary. As the dimensions get scaled down, the channel tolerances are not able to keep pace with the reduced channel dimensions. Furthermore, as the channel length decreases, operational problems associated with “short channel effect” become apparent. As is well known to those skilled in the art, short channel effects can result in threshold voltage roll-off along with increased variations in the threshold voltage and on-current of the transistors, and increased sub-threshold leakage. While sub-threshold leakage can be minimized somewhat by increasing the level of dopants used in the fabrication process, this can introduce other problems such as junction leakage and “hot electron” effects.
In an effort to overcome the physical processing limitations associated with horizontal scaling, recent research and development activities have increasingly focused on the ability to construct devices with a vertical orientation.
While various techniques have met with some limited success, there is no significant consistency in the techniques currently practiced. Vertical fabrication is expensive because it is a new technology and the fabrication processes required to produce vertical devices are not as well developed as the processes used to fabricate horizontal transistors. Many of the techniques used to produce vertical transistors are more costly than their horizontal counterparts.
Typically, to create a vertical device such as a transistor, the fabrication process creates an N+ source/drain diffusion on the bottom and a source/drain diffusion on the top of a silicon pillar. The source/drain diffusion on the bottom covers the entire base of the silicon pillar and the silicon pillar is not in direct electrical contact with the substrate. This fabrication process electrically isolates the transistor body from the substrate.
The isolation of the transistor body from the underlying substrate creates a phenomenon known as “floating body” effects and can cause certain problems that are well known to those skilled in the art. Floating body effects are also typical in a class of devices known as Silicon On Insulator (SOI) devices and include hysterisis of electrical characteristics, lower breakdown voltages, latch-up, and other related functionality and reliability problems. For example, during operation of a typical SOI transistor, electrical charges can accumulate in the transistor, until the associated electrical potential increases sufficiently to produce a shift in the threshold voltage (V
T
) of the transistor. This shift can adversely affect the operation of the circuit and introduce errors into the information being processed by the device. Depending on the tolerance level for critical errors, this may or may not be acceptable in a given circuit application. These various problems make circuit designs using vertical devices with floating bodies unacceptable for many circuit applications.
Therefore, there exists a need to provide improved processing methods for creating vertical semiconductor devices. In addition, new types of vertical device structures would allow circuit designers to further increase circuit density and improve circuit performance. Without new processing methods for creating reliable vertical semiconductor devices, the existing limitations of the presently known fabrication processes will prevent dramatic improvements in component density. This, in turn, will prevent widespread adoption of vertical scaling in integrated circuit design and fabrication processes and hinder the concomitant performance gains.
DISCLOSURE OF INVENTION
According to the present invention, a method for fabricating vertical circuit devices which include a body contact is disclosed. During the f
Gambino Jeffrey Peter
Mandelman Jack Allan
Parke Stephen Anthony
Wordeman Matthew Robert
Crane Sara
International Business Machines - Corporation
Schmeiser Olsen & Watts
Shkurko Eugene
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