Pillar process for copper interconnect scheme

Details Pillar process for copper interconnect scheme Pillar process for copper interconnect scheme

2000-06-16

2002-02-26

Utech, Benjamin L. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S700000, C438S702000

Reexamination Certificate

active

06350695

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention generally relates to an interconnection process used in semiconductor manufacturing and, more particularly, to a method using pillars to make connections between different layers of metal or conducting material in the fabrication of integrated circuits.
(2) Description of Prior Art
To improve the device speed of logic on sub-quarter micron semiconductor circuits, copper has gained popularity as an interconnect material. This takes advantage of the copper's low electrical resistivity and superior resistance to electro-migration. In order to effectively use copper as a multi-level interconnect, the dual damascene process has been developed and adopted. This process allows use of very fine conductor line widths and spaces. In a damascene process, trenches are formed in an isolation layer. The surface of the wafer is then covered with conductive material. Chemical mechanical polishing (CMP) is used to remove the conductive material not in the trenches and to planarize the surface. Typically, in a dual damascene process, both the conductor trenches and interlevel connecting vias are formed in the isolation layer, and then filled with conductive material.
Referring now to
FIG. 1
, a dual damascene process is depicted in cross-section. A substrate layer
10
is provided. The substrate layer
10
may contain underlying layers, devices, junctions, and other features covered by an insulating layer formed prior to deposition and patterning of the first conductive traces
12
. A conductive etch stop layer
14
is provided overlying the first conductive traces
12
. An isolation layer
16
overlies the entire surface.
Referring now to
FIG. 2
, an anisotropic via etch is performed leaving partially formed via holes
18
in the surface of the isolation layer
16
. Referring now to
FIG. 3
, a second anisotropic etch step is performed creating trenches
20
in the surface of the isolation layer
16
. This etch also completes the formation of via holes
18
. The conductive etch stop layer
14
prevents the second etch from attacking the first conductive traces
12
. The process may alternately etch the via holes
18
to the conductive etch stop layer
14
prior to formation of the trenches
20
.
Referring now to
FIG. 4
, a second conductive layer
22
is applied to the surface of the wafer, fining the via holes
18
and trenches
20
. Chemical mechanical polishing (CMP) is used to planarize the surface and expose the top surface of the isolation layer
16
, completing the formation of the dual damascene structure.
Using prior techniques, vias can be difficult to etch. Incomplete clearing of etch by-product residue at the bottom of narrow trenches may result in poor or open connections between the via and the conductive etch stop. Problems in filling the fine via openings with the second conductive layer may also result in high resistance via contacts. These problems may be exaggerated by the fact that etch rates increase in areas where via density is higher.
Other approaches improving interconnections exist. U.S. Pat. No. 5,512,514 to Lee teaches a method of using pillars in the creation of vias in multilevel metalization. U.S. Pat. No. 5,691,238 to Avanzino et al teaches a method using a dual and triple damascene process whereby pillars are created to complete interlevel connection. U.S. Pat. No. 5,693,568 to Liu et al. teaches a method using two conductive layers with a conductive etch stop layer between them. First all three layers are selectively etched to form the pattern for the lower conductors. The openings between the conductors are then filled with a dielectric. The upper conductive layer is then patterned and etched to form the interlevel vias. The openings in the upper conductive layer are then filled and the wafer surface covered with dielectric. The surface is planarized exposing the tops of the upper conductive layer. This process is repeated to form multiple levels of interconnection. U.S. Pat. No. 5,846,876 to Bandyapadhyay et al. teaches a method using multiple conductive levels to reduce conductor spacing while avoiding problems of increased capacitance.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide a process that allows the formation of reliable interlevel conductor connection.
Another object of the present invention is to provide a process of forming multi-level interconnection that avoids complicated cleaning of the via interface required in the conventional metal plug filling process.
Another object of the present invention is to provide a process of forming multi-level interconnection that reduces the number of process steps.
Another object of the present invention is to provide a process of forming multi-level interconnection that circumvents the problem caused by increased etch rate in areas of dense via population.
Yet another object of the present invention is to provide a process of forming multi-level interconnection using copper conductors thereby taking advantage of the low electrical resistivity and superior resistance to electromigration of copper.
These objects are achieved by using a process where conductive pillars are created to form vias prior to the deposition of inter-metal dielectric (IMD). This is in contrast to the conventional process where the IMD is first deposited followed by etching of via holes and filling the via holes with conductive metal.
In the present invention, a first conductive layer is deposited overlying a substrate containing devices, junctions and other structures formed in previous process steps covered by an insulating layer. A conductive etch stop layer is deposited overlying the first conductive layer and then patterned to form a mask for the first conductive layer. This is followed by a deposition of via metal layer overlying the entire surface.
A hard mask layer, such as silicon nitride (SiN) or silicon oxynitride (SiON), for example, is deposited and patterned to form the mask where via pillars are to be formed. Subsequent anisotropic etching forms the pillars in the via metal layer and openings in the first conductive layer.
An inter-metal dielectric (IMD) layer is deposited covering and filling both the openings in the first conductive layer and in between the via pillars. Chemical mechanical polishing (CMP) is then used to planarize the surface. The now smooth IMD layer is patterned using photoresist. Etching in the unprotected area of both the IMD and hard mask layer forms openings to the via pillars and single damascene trenches where second conductive layer lines will lie. These lines are formed by depositing the second conductive material overlying the IMD and filling the trenches followed by CMP to remove conductive material not in the trenches.


REFERENCES:
patent: 5512514 (1996-04-01), Lee
patent: 5691238 (1997-11-01), Avanzino et al.
patent: 5693568 (1997-12-01), Lia et al.
patent: 5846876 (1998-12-01), Bandyopadhyay et al.
patent: 6030896 (2000-02-01), Brown
patent: 6054389 (2000-04-01), Cheng
patent: 6140238 (2000-10-01), Kitch
patent: 6143638 (2000-11-01), Bohr
patent: 6228770 (2001-05-01), Pradeep et al.

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