Pillar CMOS structure

Details Pillar CMOS structure Pillar CMOS structure

2000-05-01

2001-07-03

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S067000, C257S069000, C257S204000, C257S206000, C257S338000, C257S350000, C257S351000, C257S357000, C257S365000, C257S366000, C257S367000, C257S368000, C257S369000, C257S370000, C257S371000, C257S511000, C438S153000, C438S154000, C438S199000, C438S209000, C438S212000, C438S213000

Reexamination Certificate

active

06255699

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
This invention relates generally to the formation of integrated structures and circuits on semi-conductor substrates and more particularly to the formation of FET structures and circuits. In even more particular aspects, this invention relates to formation of CMOS FET structures and circuits on semi-conductor substrates and especially to pillar CMOS technology which utilizes both vertical and horizontal surfaces on which to form FET devices.
BACKGROUND INFORMATION
One technique of increasing integrated circuit density on a given size semi-conductor substrate is by using vertical surfaces on which to form at least a portion of devices such as FET's. One form this takes is so-called pillar technology in which epitaxial silicon crystals or “pillars” are grown on a single silicon crystal substrate and the sidewalls of the grown epitaxial silicon “pillars”, are used to form at least part of some of the devices, thus allowing increased integrated circuit density, i.e. more devices per horizontal surface of the substrate, without necessity of reducing the layout ground rule size. This permits the use of coarser lithography as well permitting greater channel length control, both of which are desirable results in integrated circuit technology.
The present invention provides an improved technique and resulting devices in pillar CMOS technology.
SUMMARY OF THE INVENTION
According to the present invention a method of forming a pillar CMOS FET device, especially an inverter, and the device so formed is provided. The method includes the steps of forming abutting N wells and P wells in a silicon substrate and then forming N
+
and P
+
diffusions in the P and N wells respectively. A unitary pillar of the epitaxial silicon is grown on the substrate which pillar has a base at the substrate which base overlays both the N and P wells and preferably extends at least from said N
+
diffusion to said P
+
diffusion in said substrate. The pillar terminates at a distal end. An N well is formed on the side of the pillar overlying the N well in the substrate and a P well is formed on the side of the distal end of the pillar overlying the P well on the substrate and abuts the N well in the pillar. A P
+
diffusion is formed in the N well in the pillar adjacent the distal end and a N
+
diffusion is formed in the P well in the pillar adjacent the distal end. A gate insulator preferably silicon dioxide is formed over both sides of the pillar and gate electrodes are formed over the gate insulators.
In one embodiment the mask material is formed on the substrate with an opening which extends down to the substrate and mandrel or spacer material is deposited in the opening around the walls of the mask. The epitaxial silicon is grown within the opening defining the spacer material. The spacer or mandrel material is then removed and gate insulators are grown on opposite sides of the pillar followed by forming gates on opposite sides of the pillar preferably of polysilicon. In this embodiment, wiring channels can be formed at the same time as the opening in the mask material is formed and the mandrel material deposited in the channels which mandrel material is removed at the same time the mandrel is removed after the growing of the epitaxial silicon. The insulator is grown on the substrate and wiring preferably polysilicon is deposited in the channels preferably at the same time that the gate material is deposited.
In another embodiment a self-aligning process of forming the pillar where the N and P wells is provided so as to precisely align the pillar on the substrate.


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IBM Technical Disclosure Bulletin, “Structures and Layout of a New Self-Aligned Pilar CMOS Logic Gate and SRAM Cell,” vol. 32, No. 9A, Feb. 1990, pp. 338-340.*
IBM Technical Disclosure Bulletin, “New Self-Aligned Pillar CMOS Technology-Structures and Fabrication Methods,” vol. 32, No. 8A, Jan. 1990, pp. 144-145.

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