PID loop filter for timing recovery in a sampled amplitude read

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

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Details

375350, 375355, 364162, 36472401, H03D 324

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active

055725589

ABSTRACT:
A PID filter employed in a timing recovery phase-locked loop (PLL) for synchronizing the sampling of a read signal from a magnetic read head in a sampled amplitude read channel for magnetic recording. In addition to a proportional and integral term, the PID filter comprises a derivative term to decrease the settling time of the PLL by increasing the phase margin and damping. Consequently, the PLL locks onto the acquisition preamble in a shorter period thereby reducing the necessary preamble length and maximizing storage area for user data. The derivative term of the loop filter is disabled during tracking mode in order to attenuate noise in the phase error and to reduce gain variance associated with tracking arbitrary user data. The structure of the PID loop filter is transformed into an alternative structure in order to minimize the computation path latency between delay registers to avoid limiting the speed of the read channel. To defeat possible harmonic lock conditions caused by non-linearities in the phase-locked loop, a frequency error is added to the accumulation path (integrating path) of the PID filter. A further transformation provides better range and resolution for the PID filter coefficients.

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Cideciyan, Dolivo, Hermann, Hirt, Schott, "A PRML System for Digital Magnetic Recording", IEEE Journal on Selected Areas in Communication vol. 10, No.1, pp. 38-56, Jan. 1992.
Hong, Wood, Chan, "An Experimental 180 Mb/sec PRML Channel for Magnetic Recording", IBM Storage System Products Division, vol. 27, No. 6, Nov. 1991.

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