Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2002-02-15
2004-03-16
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Signals
C365S207000, C365S230030
Reexamination Certificate
active
06707729
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of semiconductor memory devices and, more particularly to a physically alternating sense amplifier activation scheme for a semiconductor memory device.
BACKGROUND OF THE INVENTION
An essential semiconductor device is semiconductor memory, such as a random access memory (RAM) device. A RAM device allows the user to execute both read and write operations on its memory cells. Typical examples of RAM devices include dynamic random access memory (DRAM) and static random access memory (SRAM).
DRAM is a specific category of RAM containing an array of individual memory cells, where each cell includes a capacitor for holding a charge and a transistor for accessing the charge held in the capacitor. The transistor is often referred to as the access transistor or the transfer device of the DRAM cell.
FIG. 1
illustrates a portion of a DRAM memory circuit containing two neighboring DRAM cells
10
. Each cell
10
contains a storage capacitor
14
and an access field effect transistor or transfer device
12
. For each cell, one side of the storage capacitor
14
is connected to a reference voltage (illustrated as a ground potential for convenience purposes). The other side of the storage capacitor
14
is connected to the drain of the transfer device
12
. The gate of the transfer device
12
is connected to a signal known in the art as a word line
18
. The source of the transfer device
12
is connected to a signal known in the art as a bit line
16
(also known in the art as a digit line). With the memory cell
10
components connected in this manner, it is apparent that the word line
18
controls access to the storage capacitor
14
by allowing or preventing the signal (representing a logic “0” or a logic “1”) carried on the storage capacitor
14
to be read to or written from the bit line
16
. Thus, each cell
10
contains one bit of data (i.e., a logic “
0
” or logic “
1
”).
Referring to
FIG. 2
, an exemplary DRAM circuit
40
is illustrated. The DRAM
40
contains a memory array
42
, row and column decoders
44
,
48
and a sense amplifier circuit
46
. The memory array
42
consists of a plurality of memory cells (constructed as illustrated in
FIG. 1
) whose word lines and bit lines are commonly arranged into rows and columns, respectively. The bit lines of the memory array
42
are connected to the sense amplifier circuit
46
, while its word lines are connected to the row decoder
44
. Address and control signals are input into the DRAM
40
and connected to the column decoder
48
, sense amplifier circuit
46
and row decoder
44
and are used to gain read and write access, among other things, to the memory array
42
.
The column decoder
48
is connected to the sense amplifier circuit
46
via control and column select signals. The sense amplifier circuit
46
receives input data destined for the memory array
42
and outputs data read from the memory array
42
over input/output (I/O) data lines. Data is read from the cells of the memory array
42
by activating a word line (via the row decoder
44
), which couples all of the memory cells corresponding to that word line to respective bit lines, which define the columns of the array. One or more bit lines are also activated. When a particular word line is activated, the sense amplifier within circuit
46
that is connected to the proper bit lines (i.e., column) detects and amplifies the data bit transferred from the storage capacitor of the memory cell to its bit line by measuring the potential difference between the activated bit line and a reference line which may be an inactive bit line. The operation of DRAM sense amplifiers is described, for example, in U.S. Pat. Nos. 5,627,785; 5,280,205; and 5,042,011, all assigned to Micron Technology Inc., and incorporated by reference herein.
The sense amplifier circuit
46
used in DRAM devices is typically arranged as banks of individual sense amplifiers. Common connections are used to activate the banks of sense amplifiers. A bank of sense amplifiers has many, e.g., two hundred and fifty-six, sense amplifiers adjacent to each other.
FIG. 3
illustrates a typical sense amplifier
46
found in a DRAM sense amplifier bank. The sense amplifier
46
includes four isolating transistors
80
,
82
,
88
,
90
, two input/output (I/O) transistors
84
,
86
, a p-sense amplifier circuit
70
and an n-sense amplifier circuit
60
.
The first isolating transistor
80
is connected such that its source and drain terminals are connected between a first sense amp line SA and a first bit line DL
a
. The first bit line DL
a
is also connected to memory cells (not shown) within the memory array
42
(FIG.
2
). Similarly, the third isolating transistor
88
is connected such that its source and drain terminals are connected between the first sense amp line SA and a second bit line DL
b
. The second bit line DL
b
is also connected to additional memory cells (not shown) within the memory array
42
(FIG.
2
). The second isolating transistor
82
is connected such that its source and drain terminals are connected to a second sense amp line SA_ and a third bit line Dl
a
—
, which during a sensing operation is typically driven to a complementary state relative to the first bit line DL
a
. The third bit line Dl
a
—
is also connected to memory cells (not shown) within the memory array
42
(FIG.
2
). The fourth isolating transistor
90
is connected such that its source and drain terminals are connected to the second sense amp line SA_ and a fourth bit line Dl
b
—
. The fourth bit line Dl
b
—
is also connected to memory cells (not shown) within the memory array
42
(FIG.
2
).
The gate terminal of the first and second isolating transistors
80
,
82
are connected to a first isolation gating line ISO
a
—
while the gate terminal of the third and fourth isolating transistors
88
,
90
are connected to a second isolation gating line ISO
b
—
. All four of the isolating transistors
80
,
82
,
88
,
90
are n-channel MOSFET (metal oxide semiconductor field effect transistor) transistors. The isolating transistors
80
,
82
,
88
,
90
and the isolation gating lines ISO
a
—
, ISO
b
—
form isolation devices. The normal state for the isolation gating lines ISO
a
—
, ISO
b
—
is a high signal. For the sense amplifier
46
that is adjacent to the selected memory array
42
, the isolating transistors
80
,
82
,
88
,
90
that do not connect directly to the selected array are driven to ground (via the isolation gating lines ISO
a
—
, ISO
b
—
). This isolates the deselected array from the active sense amplifier.
The first I/O transistor
84
is connected between a first I/O line IO and the first sense amp line SA and has its gate terminal connected to a column select line CS. The second I/O transistor
86
is connected between a second I/O line IO_ and the second sense amp line SA_ and has its gate terminal connected to the column select line CS. The I/O transistors
84
,
86
are also n-channel MOSFET transistors. The I/O lines IO, IO_ are used by the circuit
46
as a data path for input data (i.e., data being written to a memory cell) and output data (i.e., data being read from a memory cell). The data path is controlled by the column select line CS, which is activated by column decoder circuitry
48
(
FIG. 2
) of the DRAM.
The p-sense amplifier circuit
70
includes two p-channel MOSFET transistors
72
,
74
. The n-sense amplifier circuit
60
includes two n-channel MOSFET transistors
62
,
64
. The first p-channel transistor
72
has its gate terminal connected to the second sense amp line SA_ and the gate terminal of the first n-channel transistor
62
. The first p-channel transistor
72
is connected between the second p-channel transistor
74
and the first sense amp line SA. The second p-channel transistor
74
has its gate terminal connected to the first sense amp line SA and the gate terminal of the second n-channel transistor
64
. The second p-channel transistor
74
is connected between the first p-channel transistor
7
Dickstein , Shapiro, Morin & Oshinsky, LLP
Hur J. H.
Lebentritt Michael S.
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