Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-05-15
2007-05-15
Whitmore, Stacy A (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
10738278
ABSTRACT:
The matching algorithm of the layout synthesis method and apparatus disclosed locates transistor pattern matches in a design, links a parameterized tile to each identified match, and adjusts certain variable parameters of the linked parameterized tile to meet the physical design requirements of each located match. Each transistor pattern corresponds to a parameterized tile, which is an actual physical representation of the corresponding pattern and includes variable parameters, which may include transistor size. The matching algorithm locates matches in the design for an ordered list of patterns, names each located match, links the proper parameterized tile to each named match, and adjusts the tile's variable parameters as required. Transistors in the design are included in one and only one named located match.
REFERENCES:
patent: 6539533 (2003-03-01), Brown et al.
patent: 6912705 (2005-06-01), Korobkov
patent: 2003/0121019 (2003-06-01), Brown et al.
patent: 2005/0060128 (2005-03-01), Reed et al.
Hill, Dwight D., et al., “Benchmarks for cell synthesis”, 27thACM/IEEE Design Automation Conference, IEEE, 1990., pp. 317-320.
Blomgren James S.
Glowka Donald W.
Olson Timothy A.
Reed Jeffrey B.
Rudwick Thomas W.
Booth Matthew J
Intrinsity, Inc.
Matthew J Booth & Associates PLLC
Whitmore Stacy A
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