Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2000-06-20
2002-11-05
Ellis, Kevin L. (Department: 2186)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
Reexamination Certificate
active
06477634
ABSTRACT:
The field of the invention is that of computer systems, in which an operating system includes a virtual addressing mechanism, and in particular the field of physical page de-allocation processes within the operating system, to bring them into correspondence with the virtual pages used by application processes.
The prior art discloses virtual addressing mechanisms, for example the patents or patent applications U.S. Pat. No. 4279014 and FR 9801701. A virtual addressing mechanism makes it possible to make available to one or more processors of a computer a virtual memory space that is not limited by the size of the physical memory of the machine. Corresponding to a virtual page of the virtual memory space used by the machine is a physical page of the physical memory of the machine, and the numbers of corresponding pages are stored in a correspondence table. When a processor needs to use a virtual page for which there does not exist a physical page available in memory, the operating system initiates a process to de-allocate physical pages.
Various de-allocation processes are disclosed in the prior art, such as, for example, the LRU (Least Recently Used) methods, which de-allocate the physical pages that have been least recently used. This type of process is described in EP 0394115, for example.
In the prior art, to use a process of the LRU type, each line of the conversion table includes a reference indicator. When a processor accesses a virtual page number for which there exists a line of the conversion table that contains a physical page number, the processor sets the reference indicator of this line to a first state to indicate that it has just accessed this line. When it is necessary to de-allocate physical page numbers to place them in correspondence with new virtual page numbers, the de-allocation process runs through the conversion table cyclically until it finds a reference indicator that has been placed in a second state. On each line for which the de-allocation process has detected a reference indicator that has been set to the first state, the process sets it to the second state to indicate that it has just scanned this line. Therefore, when the process again scans the reference indicator of a line, the reference indicator will still be in the second state unless any processor has reset it to the first state in the meantime. The indicators that remain in the second state are the indicators of the lines that have been used less recently than those for which the reference indicator has been reset to the first state between two successive scans of this line by the de-allocation process. The reference indicator thus establishes an aging of the utilization of the line that contains it as a function of the cycle time it takes the de-allocation process to run through the conversion table, without the ability to accelerate a preferential aging of certain lines that contain page numbers to be de-allocated more rapidly than others.
This requirement may come up, for example, if it is necessary to limit the consumption of physical pages by a process by de-allocating on a priority basis the pages that have been allocated to said process. The problem that occurs is being able to give priority to the de-allocation of certain pages without thereby de-allocating the recently used pages.
The object of the invention is a process to deallocate physical pages for a virtual addressing mechanism by means of a first pointer on a first line of a conversion table that contains an indicator that has been set to a first state by a processor, whereby said process sets the indicator to a second state if the state is the first state and de-allocating said first line if the state is the second state. The process is characterized by the fact that it sets the indicator that has been set to the first state by the processor on a second line of the conversion table to the second state by means of a second pointer on the second line on the indication of an attribute value for said second line.
REFERENCES:
patent: 4279014 (1981-07-01), Cassonnet et al.
patent: 5329627 (1994-07-01), Nanda et al.
patent: 5802568 (1998-09-01), Csoppenszky
patent: 0394115 (1990-10-01), None
patent: 0788053 (1997-08-01), None
patent: 2774788 (1999-08-01), None
patent: 9418625 (1994-08-01), None
Bull S.A.
Ellis Kevin L.
Nils H. Ljungman & Associates
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