Physical layer interface device

Details Physical layer interface device Physical layer interface device

1998-03-04

2001-04-10

Chin, Stephen (Department: 2634)

Pulse or digital communications

Transceivers

C375S220000, C375S257000, C375S258000, C375S316000, C370S402000

Reexamination Certificate

active

06215816

ABSTRACT:

FIELD OF THE INVENTION
This invention generally relates to digital communications, and more particularly to a physical layer interface device.
BACKGROUND OF THE INVENTION
Local area networks (LANs) have become widely accepted and used within many and various industries as a way to interconnect many work stations and/or personal computers (PCs) to allow them to share resources such as data and applications without the need for an expensive mainframe computer and its associated multiple attached terminals. One widely accepted LAN arrangement is an “Ethernet” LAN, which is defined in the IEEE 802.3 standard.
With the widespread acceptance of LANs and the continuing acceleration of technology, the demand for LAN arrangements with higher and higher transfer rates continues unabated. Two 100 Megabit per second (Mbps) LANs are extending the reach of the installed base of 10 Mbps Ethernet LANs. Although this increased transfer rate is desired, it often comes at the expense of replacing existing 10 Mbps equipment with new more expensive 100 Mbps equipment. However, some LANs may run with both types of equipment installed. It would be convenient to have a physical layer interface device that would operate at both transfer rates.
The present invention provides a LAN physical layer interface device that is capable of operating at both transfer rates in a cost effective and versatile manner.
SUMMARY OF THE INVENTION
A single chip dual function 10 Base-T/100 Base-X physical layer interface device (PHY) compatible with existing 5V parts is provided by the present invention. The PHY includes a media-independent interface (MII) and connects to an unshielded twisted pair cable via an isolation transformer and a single RJ45 connector. The PHY includes built-in auto-negotiation circuitry that allows for automatic selection of half/full duplex 10 Base-T and 100 Base-TX, while auto-polarity correction circuitry ensures immunity to receive pair reversal in the 10 Base-T mode of operation. The PHY includes internal PLL circuitry that uses a single 20 MHz clock or crystal, but that is suitable for either speed mode. The PHY includes low-power and power down modes. The 10 Base-T portions of the PHY include smart squelch for improved receive noise immunity. The PHY includes high jitter tolerance clock recovery circuitry and transmit jabber detection circuitry. The 10 Base-T portions of the PHY include on board transmit waveshaping. The 100 Base-X portions of the PHY include synthesized rise time control for reduced electromagnetic interference (EMI). The PHY includes a programmable transmit voltage amplitude for 100 Base-X MLT-3 waveform generation and integrated adaptive equalization circuitry and baseline wander correction (DC restoration) circuitry for the 100 Base-X receiver.


REFERENCES:
patent: 5577069 (1996-11-01), Lau et al.
patent: 5598406 (1997-01-01), Albrecht et al.
patent: 5610903 (1997-03-01), Crayford
patent: 5717720 (1998-02-01), Jackson et al.
patent: 5771237 (1998-06-01), Kao
patent: 5818269 (1998-10-01), Brown et al.
patent: 5896417 (1999-04-01), Lau
patent: 5991303 (1999-11-01), Mills
patent: 6067585 (1998-06-01), Hoang

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