Physical layer device with output buffer for link pulse...

Details Physical layer device with output buffer for link pulse... Physical layer device with output buffer for link pulse...

2006-03-07

2006-03-07

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C326S026000, C370S419000

Reexamination Certificate

active

07010707

ABSTRACT:
A method for saving electrical power for a physical layer (PHY) device including a plurality of sub-circuits is disclosed. The method includes the steps of outputting a plurality of link pulses, asserting a plurality of disabling signals between two adjacent link pulses for disabling the sub-circuits, respectively, and deasserting the disabling signals for enabling the sub-circuits, respectively. The disabling signals are asserted separately for disabling the sub-circuits at different time points. A physical layer device for use in a chip for saving electrical power is also disclosed.

REFERENCES:
patent: 5632019 (1997-05-01), Masiewicz
patent: 5907553 (1999-05-01), Kelly et al.
patent: 5923183 (1999-07-01), Kim et al.
patent: 6795450 (2004-09-01), Mills et al.

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