Physical design technique providing single and multiple core...

Details Physical design technique providing single and multiple core... Physical design technique providing single and multiple core...

2000-08-24

2002-06-18

Thompson, Craig (Department: 2813)

Semiconductor device manufacturing: process

Semiconductor substrate dicing

Having specified scribe region structure

C438S401000, C438S800000, C438S017000, C438S010000

Reexamination Certificate

active

06406980

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to integrated circuit fabrication and, more particularly, to mask processing and chip design.
2. Description of Related Art
During the design of complex, highs-speed very large scale integrated circuit (VLSI) chips, such as, for example, microprocessors, trade-offs must be made for various reasons. One very important trade-off is chip size versus cost. This is a trade-off that directly influences design content. That is, highly complex microprocessors, which provide high performance, require large amounts of area, a fact that directly influences manufacturing costs exponentially. These high performance designs are then usually restricted to the high-end of the system spectrum.
However, the consumer marketplace is driven from the low-end. This means that cost is everything, even at the expense of performance. These two ideals are paradoxical for the chip design team(s). Designers, then, must focus on one spectrum or the other in a particular design cycle. This forces serialization of the design process, whereas one end of the spectrum (complex, high performance, costly or simple, low performance, cheap) is completed first, then the other is derived from the first.
In order to gain ultra-high performance, today's high performance microprocessors are now integrating multiple cores on a single chip/design (e.g., Spinnaker/Power4 Microprocessor, a product of the International Business Machines Corporation of Armonk, N.Y.). These designs are aimed at the high-end of the system spectrum. When the high-end product is completed, a lower performance, cheaper derivative is typically completed using a single core design (e.g., IBM's plan to follow Spinnaker with a single-core design). Furthermore, each of the designs may incorporate a separate on-board memory hierarchy and/or capacity. The net result of both projects is that both high and low end users/markets are satisfied. However, there is significant cost in such a serial design process because it requires, for example, all-new mask sets and manufacturing processes.
Therefore, it would be desirable to have a simple method to design and build both high and low end designs in a single step which utilize most of the same mask sets. Such a process would allow the introduction of both high end and low end products in a manufacturing process that is less serialized and in a manner that utilizes less manufacturing resources than is found using current methods. Such a single step method would lead to lower cost for both the low end and high end designs.
SUMMARY OF THE INVENTION
The present invention provides a wafer design layout and method of producing multiple integrated chip types using a single set of masks for a wafer and then at the time the type of chip desired is known, using a few customizing steps to produce the final integrated chip. In one embodiment, the wafer layout includes a plurality of groupings of components and a plurality of dicing channels separating each of the components from others of the components. After the particular type of integrated circuit chip desired is selected, the wafer may then have the final few layers processed and the chips removed using the appropriate dicing channels for the integrated circuit chip desired.


REFERENCES:
patent: 6020217 (2000-02-01), Kuisi et al.

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