Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-04-23
2004-11-23
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06823496
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention describes a system and method for locating and defining process sensitive sites isolated to specific geometries or shape configurations within the chip design data, also leveraging the knowledge of the process sensitive sites found. Process sensitive sites are defined as those areas where the design assumptions and expectations have exceeded the actual process capability.
Electrical shorts and opens parameters are impacted where the process tolerance is not design compatible. This systematic yield loss may be driven by RIE loading effects, lithographic offsets, over/under layout sensitivities, topography, pattern density, and other adjacency effects, at specific process sensitive sites. Given the compression of the yielding production ramp-up cycle, design revisions with work in progress turns are no longer an option.
Fabricators and designers commonly use tools or systems for placing shapes to improve layout sensitivity and optimize for random defect tolerance. For example, wiring layout tools will not only optimize routing for timing and reduced delay, but also to modulate defect tolerance. The defect tolerance may be analyzed by critical area versus defect size computation or optionally analyzed by the distance and run length between conductive wires susceptible to random particles. Fabricators also use tools and systems for design rule and shapes checking. Another standard methodology to compute random photo yield includes throwing random defects at-level, generating faults at the random defect sites, then selecting the faults with shape checking programs. Yield is a function of the number of faults and the size distribution.
Systematic process defects are modulated with the use of automated tools or systems to place dummy shapes or slots, place additional redundant vias or contacts or other redundant elements, and to perform layout modifications for lithographic proximity corrections, and for other RIE and lithographic effects. In the semiconductor industry, these design-for-manufacturing activities are paired with other product or design complexity analyses such as total length of routed wires, and single via count data, for example.
Computer aided design analysis tools are also utilized in industry and integrated with manufacturing and test simulators such that circuit designers can understand the impact of design issues on manufacturability of test processing.
However, the inventors are not aware any tools or systems looking for sensitivities related to structures or process and layout incompatibilities, and leveraging that information as feedforward to the designer, as well as leveraging that information in manufacturing process controls methodologies, as is described above.
SUMMARY OF THE INVENTION
Therefore, a goal of this physical design characterization system is to improve the technology product development and the probability of first time fabrication success for new products and partnumbers. Once a systematic process sensitive site is identified, 3D design checking decks are coded and executed on the physical design data. Checking deck jobs are triggered and processed for each new chip design when it is introduced into the fabricator. Specific geometries and configurations in areas of known or potential layout sensitivities are identified as chip coordinates to the owner and design team. Pictures of partnumber specific process sensitive sites are captured along with dimensional layout description and sent to a web site library for easy reference and analysis.
This physical design characterization system can be used to identify a set of manufacturing physical design challenges for new partnumbers, the reference tool may be used to provide solution insights, it may be used to update tactical projections and floor plans, and the reference retains technology learning which can be reapplied to next technologies. It can also be used to improve design for manufacturing compliance, and used for resource management or prioritization correlated to difficult design partnumbers or sectors.
All the above results in improved serviceability, avoidance of production stoppage and scrap, and measurable time-to-profit achievements.
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Bergman Reuter Bette L.
DeHond Mitchell R.
Leipold William C.
Maynard Daniel N.
Pfeifer Brian D.
Bowers Brandon
International Business Machines - Corporation
Kotulak Richard M.
Siek Vuthe
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