Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-06-07
2005-06-07
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06904582
ABSTRACT:
A photomask for reducing power supply voltage fluctuations in an integrated circuit and integrated circuit manufactured by the same are disclosed. The photomask includes a substrate and a patterned layer formed on at least a portion of the substrate. The patterned layer may be formed using a mask pattern file created by analyzing a pattern in a mask layout file to identify a region in the pattern to add one or more decoupling capacitors. Once the region is identified, a feature located in the identified region is moved based on a design rule from a first position to a second position in the mask layout file to create a space in the identified region. The decoupling capacitors are placed in the space in the identified region.
REFERENCES:
patent: 6446016 (2002-09-01), Zhu
patent: 6487702 (2002-11-01), Lin et al.
patent: 6523159 (2003-02-01), Bernstein et al.
patent: 6618843 (2003-09-01), Dansky et al.
patent: 2002/0166109 (2002-11-01), Rittman et al.
patent: 2004/0064800 (2004-04-01), Korobkov
patent: 2004/0073881 (2004-04-01), Nassif et al.
U.S. Appl. No. 10/378,537 entitledSystem and Method for Generating a Mask Layout File to Reduce Power Supply Voltage Fluctuations in an Integrated Circuitfiled by Rittman, et al., on Mar. 3, 2003; 49 pages.
Oren Micha
Rittman Danny
Baker & Botts L.L.P.
DuPont Photomasks, Inc.
Siek Vuthe
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