Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-07-12
2003-03-04
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S300000, C257S355000
Reexamination Certificate
active
06528836
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to semiconductor technology, and more specifically to photomask protection from electrostatic damage and to a pod provided with such protection. Even more specifically, the invention relates to a photomask and a pod designed to perform active ESD protection.
2. Description of the Related Art
In the fabrication of semiconductor devices and integrated circuits (IC), electrostatic discharge (ESD) is a phenomenon that commonly occurs during the handling of semiconductor integrated circuit (IC) devices and one of the main factors causing IC damage that may turn into a very critical problem immediately affecting stable yield and smooth production.
As an example, the static electricity problem may arise when one walks on a carpet with semi-conductor wafers. Electrostatic voltage of about a few hundred volts may exist on one's body and wafers if relative humidity is high. With humidity being at its low, the electrostatic voltage may reach as high as about a few thousand volts. If a conductive object occasionally contacts the wafers, a strong ESD could occur and damage the ICs on the wafers. ESD is an especially serious problem for fabrication of a complementary metal-oxide semiconductor (CMOS) device.
Damage due to electrostatic charge, which may accumulate for various reasons and produce potentially destructive effects on an IC device, typically can occur during a testing phase of the IC fabrication or during assembly of the IC onto a circuit board, as well as during use of equipment, into which the IC has been installed. Damage to a single IC due to poor ESD protection in an electronic device can partially, or sometimes completely, hamper its functionality. ESD protection for semiconductor ICs is, therefore, a reliability issue.
Also, in high-resolution lithography, the dust is often attracted to the mask by static electricity, and, due to dust collecting on the mask, resolution impairment sometimes occurs. The solution proposed is to coat the entire photomask with a transparent, electrically conductive coating. The coating is electrically grounded to drain static charge. Conductive materials are often used for lithographic masks, but the patterns cannot be grounded effectively because of island regions existing in the pattern. If the pattern is itself conducting, then there is the added option of applying the antistatic layer under the pattern. If the pattern is formed of a photographic emulsion of a patterned photoresist, it is protected from damage and wear in handling by the harder conductive coating.
In one more aspect of the problem, it is to be understood that with the progress of the industry, technological dimensions of semiconductor devices and ICs become increasingly smaller. For example, a thinner gate oxide layer is necessary as the device integration increases. This causes that a gate-oxide breakdown voltage is approaching a junction breakdown voltage of a field effect transistor or even less. In addition, circuit architecture is usually designed by minimum design rules, in which a sufficient distance between a contact and a diffusion-region edge, or a contact and a gate edge may not be properly considered and designed. The result is that devices in high integration have poor performance to resist a substantial electrostatic transient current, and wafers are therefore damaged by the ESD phenomenon. In using photolithography, design rule shrinking causes even smaller mask pattern line spacing, and the ability of the mask to hold out against static electricity damage is becoming even weaker. Static electricity induce point discharge between the narrower lines, damage this pattern of lines and make them short. This is especially true for fabrication of a deep sub-micron IC.
In order to protect wafers from ESD damage, many methods to solve the ESD problem have been proposed. ESD stress models have been developed which are based on the reproduction of typical discharge pulses to which the IC may be exposed during manufacture or handling. Three standard models, known as the Human Body Model (HBM), Machine Model (MM), and Charged Device Model (CDM) have been developed. The human-body model is set forth in U.S. Military Standard MIL-STD-883, Method 3015.6. This Military Standard models the electrostatic stress produced on an IC device when a human carrying an electrostatic charge touches the lead pins of the IC device. The machine model is set forth in Industry Standard EIAJ-IC-121, which describes the electrostatic stress produced on an IC device when a machine carrying an electrostatic charge contacts the lead pins of the IC device. The charged device model describes the ESD current pulse generated when an IC device already carrying an electrostatic charge is grounded while being handled.
Typically, the most common conventional method is to make an ESD protection circuit between input/output (I/O) pads and internal circuits including a coupling-type diode or a coupling-type metal-oxide semiconductor (MOS) device so that the ESD does not damage the ICs fabricated on the wafers. However, those protection circuits are power consuming and cannot endure a larger ESD stress. The gate-oxide thickness becomes small, as device integration gets high, resulting in a low gate-oxide breakdown voltage. If the gate-oxide breakdown voltage is as low as about the source/drain junction breakdown voltage, the ESD protection ability is severely degraded.
The conventional design for preventing ESD damage may also be illustrated by a prodigious network that, for the most part, involves locating a protection circuit between the input/output pads and the VSS terminal, between the input/output pads and the VDD terminal, and between the VSS and VDD power rails. Accordingly, such a prodigious network consumes a great amount of layout area, especially when used in a configuration including multi-power buses. Moreover, no ESD protection is provided between any two IC pads using the conventional design. Thus, ESD stress arising between two IC pads is only indirectly bypassed via the protection circuit located between the VSS and VDD power rails.
Beside the above-mentioned ESD-related problems and the elaborate efforts spent to protect IC from static electricity, one more problem of this sort exists that may also be fraught by destructive damage to IC components. In the semiconductor fabrication process, a square cross-sectional or rectangular cross-sectional container (a pod) made of plastic material is frequently used to transport articles. These articles may include silicon wafers, reticles, or other substrates used for building IC devices. (By reticle, a transparent ceramic substrate is understood that is coated with a metallic layer forming a pattern for an electronic circuit. The reticle is generally used in an imaging step during a photolithographic process where a pattern of a circuit is reproduced on the surface of an electronic substrate, i.e., on a wafer surface.)
A reticle can be made of any suitable transparent ceramic material. One of the most commonly used materials is quartz (a silicon dioxide). A quartz reticle can be readily coated with a chrome layer at selective areas to reproduce an electrical circuit. The chrome metal layer may be formed of either pure chromium or a chromium alloy. During a photolithographic imaging process, light from a light source is projected from one side of the reticle that is coated with the pattern such that the pattern can be reproduced on the surface of a wafer, which is positioned on the opposite side of the reticle. The pattern for the electronic circuit coated on the reticle is frequently laid out in a 5× magnification. The true dimensions of the electronic circuit reproduced on the wafer surface can be obtained by suitably adjusting the optical lenses placed between the reticle and the wafer. Metallic coatings other than chrome may also be put on the surface of the reticle for the circuit layout. However, chrome has been found to be an ideal materi
Berry Renee R.
Taiwan Semiconductor Manufacturing Co. Ltd
Tung & Associates
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