Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-06-03
2004-08-24
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06782524
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates in general to the field of photolithography, and more particularly to a photomask and method for eliminating design rule violations from the photomask.
BACKGROUND OF THE INVENTION
Over the past several years, the number of transistors in a semiconductor device has increased dramatically. Due to this increase, the time to design and manufacture semiconductor devices has also increased.
A typical semiconductor design process includes numerous steps. Initially, a circuit designer prepares a schematic diagram that includes logical connections between logic elements that together form an integrated circuit. The schematic diagram is then tested to verify that the logic elements and associated logical connections perform a desired function. Once the circuit is verified, the schematic diagram is converted into a mask layout database that includes a series of polygons. The polygons may represent the logic elements and the logical connections contained in the schematic diagram. The mask layout database is then converted into multiple photomasks, also know as masks or reticles, that may be used to image different layers of the integrated circuit on to a semiconductor wafer.
Typically, the mask layout database is created manually by a layout designer or automatically by a synthesis tool. Once the mask layout database is complete, spacing between the polygons on the same layer is compared to the minimum allowable spacing that is included in a technology file for a desired manufacturing process. This comparison may identify design rule violations if the spacing between the polygons or the dimensions of the polygons in the mask layout database is less than the corresponding minimum allowable design rule in the technology file.
Today, any design rule violations in the mask layout database are corrected manually by a layout designer. The layout designer typically finds each violation and manually corrects the violations by moving polygons associated with the violations. During the correction process, the layout designer may create new design rule violations and, therefore, the correction process may be repeated until the mask layout database does not include any design rule violations. The process of iteratively correcting the design rule violations may take several hours or even days to complete and can increase the time needed to design the integrated circuit. The additional time required to complete layout may also delay the production of a photomask set used to fabricate the integrated circuit.
SUMMARY OF THE INVENTION
In accordance with the present invention, the disadvantages and problems associated with eliminating design rule violations on a photomask have been substantially reduced or eliminated. In a particular embodiment, a photomask is formed by using a mask pattern file created by automatically correcting a design rule violation in a mask layout file.
In accordance with one embodiment of the present invention, a photomask includes a patterned layer formed on at least a portion of a substrate. The patterned layer may be formed using a mask pattern file that is created by comparing a feature dimension in a mask layout file with a design rule in a technology file. If the feature dimension is less than the design rule, a design rule violation is identified and automatically corrected in the mask layout file.
In accordance with another embodiment of the present invention, an integrated circuit includes a plurality of interconnect layers, including but not limited to n-well, p-well, diffusion, polysilicon and metal, and a plurality of contact layers that provide electrical connections between the respective interconnect layers. The interconnect and contact layers may be formed using a plurality of photomasks that are created by comparing a feature dimension in a mask layout file with a design rule in a technology file. If the feature dimension is less than the design rule, a design rule violation is identified and automatically corrected in the mask layout file. A plurality of mask pattern files that correspond to the interconnect and contact layers are generated from the mask layout file.
Important technical advantages of certain embodiments of the present invention include a design rule fix (DRF) tool that reduces the design time for an integrated circuit. A design rule check (DRC) tool checks a mask layout file for design rule violations and identifies any violations in an output file. If the mask layout file contains design rule violations, the DRF tool reads the coordinates of the violation from the output file and automatically adjusts a feature dimension associated with the violation until the feature dimension is equal to or greater than a minimum design rule for a desired manufacturing process. The time needed to verify the mask layout file may be substantially reduced because the DRF tool simultaneously identifies and eliminates the design rule violations in the mask layout file.
Another important technical advantage of certain embodiments of the present invention includes a DRF tool that reduces the size and increases the density of features in a mask layout file. In addition to correcting design rule violations, the DRF tool determines if the spacing between polygons in the mask layout file is greater than the corresponding minimum design rules in a technology file and reduces the spacing until it is approximately equal to the minimum design rule. The density of the mask layout file, therefore, may be increased, which also increases the number of integrated circuits that may be fabricated on a wafer.
All, some, or none of these technical advantages may be present in various embodiments of the present invention. Other technical advantages will be readily apparent to one skilled in the art from the following figures, descriptions, and claims.
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Hsiao et al.; A rule-based compactor for VLSI/CAD mask layout; IEEE Computer software & Applications Conf.; pp. 35-42; Oct. 1988.
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U.S. patent application Ser. No. 10/159,566 entitledSystem and Method for Correcting Design Rule Violations in a Mask Layout Filefiled by Rittman on May 31, 2002; 38 pages.
Baker & Botts L.L.P.
Bowers Brandon
DuPont Photomasks, Inc.
Garbowski Leigh M.
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