Photolithographic process for preventing corner rounding

Details Photolithographic process for preventing corner rounding Photolithographic process for preventing corner rounding

2000-11-22

2001-11-13

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Introduction of conductivity modifying dopant into...

Ion implantation of dopant into semiconductor region

C438S947000

Reexamination Certificate

active

06316340

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a photolithographic process in semiconductor manufacturing. More particularly, the present invention relates to a photolithographic process capable of preventing the rounding of the corners in a pattern.
2. Description of Related Art
Following the rapid increase in the level of integration, integrated circuits are now designed with decreasing feature dimensions. In the fabrication of semiconductors, one very important manufacturing step is photolithographic process. All metal-oxide semiconductor (MOS) devices related processes such as thin film patterning or dopants implantation are conducted by performing photolithographic processes. Ultimately, the fabrication of integrated circuits with a line width smaller than 0.18&mgr;m depends on the future development of photolithography. To reduce size of semiconductor devices, resolution of photomask in photolithographic process must be increased. Recent development in this direction includes optical proximity correction (OPC) and phase shift mask (PSM).
Optical proximity correction is at present one of the principle methods of eliminating critical dimension deviation due to proximity effect. Proximity effects occur when a light beam passing through a photomask with a pattern thereon is projected onto the surface of a silicon chip. In the process, the light rays may be diffracted by the photomask so that a portion of the light rays may diverge. Furthermore, some of the light passing into the photoresist layer above the silicon chip may be reflected by the semiconductor substrate of the silicon chip to cause interference. Hence, a portion of the photoresist layer may be repeatedly exposed leading to undesirable variation in photoresist exposure.
FIG. 1A
is a top view of a conventional photomask with a trench array pattern for manufacturing trench capacitors.
FIG. 1B
is a top view of the pattern on a silicon wafer after photolithographic processing with the photomask shown in FIG.
1
A.
As shown in
FIG. 1A
, a trench pattern
102
is formed on a photomask
100
. For example, if the trench pattern
102
is a trench pattern for forming trench capacitors, width
102
a
and length
102
b
of separation between neighboring trenches are different. In other words, pattern density in the horizontal and the vertical directions are different and hence corresponding intensity and strength of exposure requirements are different. Due to proximity effect, differences in the edge length and edge width of the trenches will limit the process window of the photolithographic process.
In addition, due to proximity effect, the corners of pattern is somewhat rounded leading to pattern distortion when the trench pattern
102
on the photomask
100
is transferred to the silicon wafer
104
to form an opening pattern
106
.
To reduce proximity effect, subsidiary patterns are often formed around the trench pattern on the photomask. However, as device dimensions shrink and the level of integration increases, line width becomes increasingly narrow and there is limited area around the device pattern for forming a subsidiary pattern. Consequently, cost of fabricating the photomask is increased. Moreover, as line width of a pattern shrinks, the limited resolution of a stepping machine will further reduce the process window for forming an opening pattern on a silicon wafer using photolithographic process.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a photolithographic process for preventing the rounding of the corners of a pattern. The process includes the following steps. First, a silicon wafer is provided. A first photoresist layer is formed over the silicon wafer and then patterned to form a first group of mutually parallel photoresist lines along a first direction. Thereafter, a second photoresist layer is formed over the silicon wafer and then patterned to form a second group of mutually parallel photoresist lines along a second direction. The first direction and the second direction are on the same plane but mutually perpendicular.
Since mutually perpendicular first and second group of photoresist lines is formed in separate processes, the pattern formed by the first and the second group of photoresist lines is different from a conventional opening pattern. Hence, the rounding of corners due to proximity effect will be prevented and the difficulties in producing subsidiary pattern around fine and highly integrated pattern using optical proximity correction method will be minimized. In some cases, even the subsidiary pattern is no longer required on a photomask.
In addition, separately formed first and second photoresist lines has a resolution much higher than the resolution of an opening pattern formed by a direct conventional process. Moreover, a photomask having a linear pattern will have smaller exposure diffraction and a larger depth of focus when transferring the linear pattern to a photoresist layer. Hence, a larger process window for photolithography is obtained.
After the patterned first photoresist lines has undergone such processes as soft-baking, light-exposure, post-exposure baking and photoresist-developing, there is very little intermixing with subsequent patterning of the second photoresist lines. Therefore, using this type of multiple resist pattern stacking method to form a series of mutually perpendicular pattern of photoresist above a silicon wafer, corner rounding and pattern distortion due to proximity effect can be avoided.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5124927 (1992-06-01), Hopewell et al.
patent: 5413898 (1995-05-01), Kim et al.
patent: 5756256 (1998-05-01), Nakato et al.
patent: 5955244 (1999-09-01), Duval

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