Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-06-14
2002-06-18
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S291000, C257S461000, C257S463000
Reexamination Certificate
active
06407417
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to a photoelectric conversion device having a solid-state imaging device and a light receiving elements such as a photocoupler and a method of manufacturing the same, and, in particular, the present invention relates to techniques suitable for use in an active XY addressing type solid-state imaging devices among solid-state imaging devices (so-called CMOS sensors) compatible with the CMOS manufacturing process.
2. Background Art
Conventional solid state iamging device of a transfer layer method which transfer photoelectrically converted signal charges, are classified into MOS-type and CCD-type. These solid state imaging devices, in particular CCD-type solid state imaging devices, have been recently used for camera and VTR units, digital cameras, facsimile systems, etc., and technical development is now under way for improving the characteristics.
The CCD sensor is a type that has a photoelectric conversion portion in which photoelectric transducers corresponding to pixels are arranged in a two-dimensional array, and sequentially reads signals of each pixel which have been converted into electric charges by the photeoelectric conversion portion, with a vertical transfer CCD and a horizontal transfer CCD.
The CMOS sensor does not use a CCD for vertical and horizontal transfer, and reads pixels selected by a selection line constituted by aluminum lines or the like, as with a memory device.
Here, the CCD sensor requires a plurality of positive and negative power supply potentials, while the CMOS sensor can be driven by a single power supply, enabling lower power consumption and lower voltage compared to the CCD sensor.
Moreover, since the CCD sensor uses a special process, it is difficult to directly apply the CMOS circuit manufacturing process thereto. On the other hand, the CMOS sensor uses the CMOS circuit manufacturing process. Hence it is possible to form a logic circuit, an analog circuit, an analog to digital conversion circuit or the like at the same time, by means of a CMOS process widely used in processors, semiconductor memories such as DRAMs, logic circuits, etc. That is, the CMOS sensor can be formed on a semiconductor chip the same as that for semiconductor memories and processors, and can share the production line with semiconductor memories and processors. One example of an image sensor which is such a CMOS sensor is shown in FIG.
13
.
In
FIG. 13
, reference numeral
100
denotes an image sensor (CMOS sensor). This CMOS sensor
100
is provided with a timing generation portion
102
, an image sensor portion
101
, a vertical scanning portion
103
and a horizontal scanning portion
104
for selecting an output of a pixel, an analog signal processing portion
105
, an A/D portion (A/D conversion portion)
109
for performing analog to digital conversion, a digital signal processing portion
107
for converting the digitalized signal into an output signal, and an interface portion (IF portion)
108
for outputting digital image data to the outside and receiving command data from the outside.
The image sensor portion
101
is an aggregate of basic cells of the CMOS sensor, as described later. The vertical scanning portion
103
is for controlling the vertical scanning of the basic cells in the image sensor portion
101
, and the horizontal scanning portion
104
is for controlling the horizontal scanning of the basic cells in the image sensor portion
101
. These portions perform respective scanning control with a timing signal output from the timing generation portion
101
.
The analog signal processing portion
105
subjects the image signal read from the image sensor portion
101
to required processing and outputs the signal to the A/D conversion portion
109
. The A/D conversion portion
109
then converts the image signal into a digital signal and outputs the signal to the digital signal processing portion
107
, which in turn outputs the image signal to the interface portion
108
.
The interface portion
108
can output to the outside the digital image data output via the digital signal processing portion
107
, and can also input commands from the outside. As a result, the respective constituents are controlled so as to perform control corresponding to the received commands to enable control of the mode and the output signal form of the image sensor
100
and the signal output timing, corresponding to the commands.
Here, the A/D conversion portion
109
, the digital signal processing portion
107
, and the interface portion
108
constitute a logic circuit portion
106
. Moreover, the digital signal processing portion
107
includes a memory portion. The memory portion may be constructed such that this stores image data for one or a plurality of lines, one or a plurality of blocks and one or a plurality of frames, required for the signal processing, with these being utilized for the signal processing in the digital signal processing portion
107
.
Next, a conventional basic cell in the image sensor portion
101
of the CMOS sensor
100
is shown in FIG.
14
A. In
FIG. 14
, reference numeral
10
denotes a basic cell (CMOS sensor),
11
denotes a p-type semiconductor substrate,
12
denotes a p-type well layer formed on the p-type semiconductor substrate,
14
denotes an n+ type region serving as a photodiode (photoelectric conversion region),
13
denotes a p+ type semiconductor region serving as a device separation region that separates the photoelectric conversion region
14
from an adjacent portion,
15
denotes an n+ type semiconductor region serving as a drain of a control MOSFET,
21
denotes the control MOSFET,
22
denotes a MOSFET of a source follower amplifier,
23
denotes a MOSFET of a horizontal selection switch,
24
denotes a load MOSFET of the source follower amplifier,
25
denotes a dark output transfer MOSFET,
26
denotes a light output transfer MOSFET,
27
denotes a dark output accumulation capacitance, and
28
denotes a light output accumulation capacitance.
In the p-type semiconductor substrate
11
, as shown in
FIG. 14
, the photoelectric conversion region
14
is connected to a gate of the MOSFET
22
constituting the source follower amplifier via a wiring layer (not shown), and to the source or drain of the MOSFET
22
is connected a source or drain of the MOSFET
23
serving as the horizontal selection switch. Then, to the source or drain of the MOSFET
23
is connected a source or drain of the load MOSFET
24
forming the source follower amplifier. To the source or drain of both of the MOSFET
23
and MOSFET
24
are respectively connected a source or drain of the dark output transfer MOSFET
25
and the light output transfer MOSFET
26
, and to the source or drain of the dark output transfer MOSFET
25
and the light output transfer MOSFET
26
are respectively connected the dark output accumulation capacitance
27
and the light output accumulation capacitance
28
.
The CMOS sensor having such a construction operates as described below.
That is, at first, as shown in
FIG. 14B
, a control pulse Ø
R
for the control MOSFET
21
is turned to a high level, and the n+ type semiconductor region
15
is set to a power supply voltage VDD, to reset the signal charge of the photoelectric conversion region
14
. Then, as shown in
FIG. 14C
, the control pulse Ø
R
for the control MOSFET
21
is made a low level voltage for preventing blooming.
During the signal charge accumulation, when due to the incident light, electron-hole pairs are generated in the region under the photoelectric conversion region
14
, electrons accumulate in the depletion layer under the photoelectric conversion region
14
, and holes are discharged through the p-type well layer
12
. Here, in
FIG. 14C
, the region shown by grid-like hatching, having a potential deeper than the power supply voltage VDD shows that the region is not depleted. Since there is formed a potential barrier B by means of the control MOSFET
21
, between the depletion layer formed in the p-
Nagata Tsuyoshi
Nakashiba Yasutaka
NEC Corporation
Ngo Ngan V.
Scully Scott Murphy & Presser
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