Photo-thermal induced diffusion

Details Photo-thermal induced diffusion Photo-thermal induced diffusion

2002-09-23

2003-11-04

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Radiation or energy treatment modifying properties of...

C438S613000, C438S614000, C438S740000, C438S741000, C438S975000

Reexamination Certificate

active

06642158

ABSTRACT:

BACKGROUND
1. Technical Field
An embodiment of the invention relates to semiconductor package and printed circuit board (PCB) manufacturing, and in particular relates to diffusion of a portion of one material into another.
2. Description of the Related Art
In the fabrication of integrated circuits, semiconductor wafers are processed and sliced into dice. Each die may then be mounted to a supporting structure such as a package substrate and/or a PCB for use in an electronic device. Forming the dice generally involves depositing layers of varying purposes. For example, an inter-layer dielectric (ILD) may be deposited and patterned to hold and electrically isolate conductive circuit features. The circuitry of the die includes layers of such features.
Once the die is formed, it is packaged. The packaging process may include connecting the die to a protective package substrate, which in turn may be connected directly to the PCB. The package substrate may include bond pads which are coupled to an array of metal bumps or other conductive features of the compact die. The bond pads are in turn coupled to the internal circuitry of the package substrate. In this manner, the larger package substrate may act as an electronic interface to fan out electronic paths between the compact internal circuitry of the die and the much larger PCB.
Similar to die formation, package substrate and PCB processing may include forming the above-indicated circuitry of the package substrate. Such circuitry may include multiple layers of circuit features. Similar to die circuit features, package substrate circuit features may include metal traces isolated within an interlayer dielectric layer (ILD) or metal traces on the package/PCB surface. In order to form layers of circuitry in the package substrate, a time consuming multi-step process, which may include one or more processes of metal deposition, photolithographic patterning and developing, and etching is generally employed as described below.
Initially, a dielectric core material having one or more metal layers for a package substrate may be provided having a protective coating thereon. The protective coating may be an organic material to prevent oxidation of the metal layer or a second metal layer covering some or all of the primary metal layer prior to processing. The composite core and metal layers may undergo initial processing, such as via formation prior to the formation of circuitry or addition of layers of dielectric and/or circuitry. The protective coating may then be mechanically or chemically removed, followed by deposition of dielectric material layers to support circuitry as noted above.
Metal traces or other circuit features may be patterned into, and isolated by, the dielectric material. This may be achieved by photolithographic patterning and developing. First, a resist layer is placed above the dielectric material. The resist layer may be of photosensitive material that undergoes a photomasking operation. The photomasking operation delivers a pattern of light energy (such as ultraviolet light) to the resist layer, which is then developed to selectively remove portions of the resist in accordance with the exposure pattern. Subsequently, an etchant chemical may be delivered to the package substrate, etching trenches into the dielectric material at locations where it is not protected by the resist material (i.e. where the resist has been removed by the photomasking operation). This may be followed by metalization, wherein metal lines or other circuit features are formed in the trenches.
Unfortunately, a high cost is incurred and throughput is limited by the time consuming process described above. Furthermore, material expenses are incurred by the need for a host of materials, such as those indicated above, in order to form even a single metal circuit feature of a single circuit layer.


REFERENCES:
patent: 5821627 (1998-10-01), Mori et al.

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