Phased sense amplifiers

Details Phased sense amplifiers Phased sense amplifiers

1999-08-06

2000-07-04

Tran, Andrew Q.

Static information storage and retrieval

Read/write circuit

Differential sensing

365207, 365205, 365222, 365227, 365233, 365194, 365196, G11C 708

Patent

active

060848111

ABSTRACT:
A sensing arrangement (100) for a dynamic random access memory (DRAM) is disclosed. The sensing arrangement (100) includes a sense amplifier bank (104) that is logically divided into a number of sense amplifier groups (106-1 to 106-2.sup.m). In a read operation, a given number of memory cells are coupled to the sense amplifier bank (104), and one sense amplifier group will provide read data while the remaining sense amplifier groups will refresh memory cell data. A timing circuit (102) receives a timing signal (EVAL) and address information (A1-Am) and in response thereto, enables the sense amplifier group that provides read data before the sense amplifier groups that refresh memory cell data. Peak current is reduced and improved sensing speed result.

REFERENCES:
patent: 4813021 (1989-03-01), Kai et al.
patent: 5485430 (1996-01-01), McClure
patent: 5596545 (1997-01-01), Lin
patent: 5646892 (1997-07-01), Masuda et al.
patent: 5848001 (1998-12-01), Kim
patent: 6009031 (1999-12-01), Te

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