Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Rectangular or pulse waveform width control
Reexamination Certificate
2002-09-12
2004-01-20
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Rectangular or pulse waveform width control
C327S172000
Reexamination Certificate
active
06680637
ABSTRACT:
CROSS-REFERENCES TO RELATED APPLICATIONS
This application relies for priority upon Korean Patent Application No. 2001-80484, filed on Dec. 18, 2001, the contents of which are herein incorporated by reference in their entirety.
FIELD
The present invention relates to semiconductor integrated circuits and, more particularly, to a phase splitter circuit for effectively correcting a duty cycle of a clock signal.
BACKGROUND
It is well known that a phase splitter circuit receives one input signal (e.g., a clock or data signal) to output two output signals (e.g., clock or data signals) having a phase difference of 180°. Such a phase splitter circuit has been used to control, for example, a switch of a pipeline, a double data rate signaling, and a transmission gate circuit. Output signals of an ideal phase splitter circuit have a 50% duty cycle, respectively. No skew exists between the output signals of the ideal phase splitter. Here the “skew” means a delay time difference between output signals.
Examples of a phase splitter circuit are disclosed in U.S. Pat. No. 5,874,845 entitled “NON-OVERLAPPING CLOCK PHASE SPLITTER”, U.S. Pat. No. 6,292,042 entitled “PHASE SPLITTER”, and Korea Laid-Open Patent Publication No. 1998-023059 entitled “ODD NUMBER DIVIDER CIRCUIT.”
A well-known phase splitter circuit has two signal paths (or signal transmission paths) that are constructed to generate a pair of clock signals. One of the two signal paths includes an odd number of inverters, and the other includes an even number of inverters. One clock signal is concurrently applied to both signal paths of the phase splitter circuit. For example, as shown in
FIG. 1
, a first signal path includes two inverters INV
1
and INV
2
and outputs a first output signal OUT having the same phase as an input signal IN. A second signal path includes three inverters INV
3
, INV
4
, and INV
5
and outputs a second output signal OUTN having a phase difference of 180° with respect to the input signal IN. Each of the inverters constituting respective signal paths may comprise PMOS and NMOS transistors that are connected by a manner well known in the art.
In case of the phase splitter circuit shown in
FIG. 1
, the circuit construction is so simple that the layout area is small and the power consumption is low. However, the phase splitter circuit is easily influenced by noise resulting from the parasitic load (illustrated as a resistance element and a capacitance element in
FIG. 1
) or noise resulting from process, voltage, and temperature variations (hereinafter referred to as “PVT” variation). More specifically, as the PVT condition is changed, pull-up and pull-down characteristics of construction components of the phase splitter circuit are changed. Thus, a duty cycle of respective output signals OUT and OUTN of the phase splitter circuit, or a skew between the output signals OUT and OUTN, may be changed. Further, as the parasitic load is changed, the duty cycle of the respective output signals OUT and OUTN of the phase splitter circuit, or the skew between the output signals OUT and OUTN, may be changed. In case of the phase splitter circuit shown in
FIG. 1
, when the duty cycle and the skew are changed, a changed duty cycle of an output signal, and a changed skew between the output signals OUT and OUTN, cannot be corrected into a required value.
SUMMARY
An object of the present invention is to provide a phase splitter circuit capable of securing a stable duty cycle for the change of a parasitic load and a PVT condition.
Another object of the invention is to provide a phase splitter circuit capable of suppressing a duty cycle change and a skew noise that are caused by a change of the parasitic load and/or the PVT condition.
Yet another object of the invention is to provide a phase splitter circuit capable of correcting duty cycle and skew with the use of output data.
Still another feature of the invention is to provide a phase splitter circuit capable of securing a stable duty cycle even though the duty cycle of the input signal is changed.
According to one aspect of the invention, a phase splitter circuit includes first and second signal transfer paths and a duty cycle correction circuit. The first signal transfer path receives an input signal to output a first output signal, and a second signal transfer path receives the input signal to output a second output signal with an inverted phase with respect to the first output signal. The duty cycle correction circuit operates responsive to the first and second output signals. The duty cycle correction circuit controls pull-up and pull-down speeds of the first and second signal transfer paths in the opposite directions in response to the first and second output signals, so that each of the first and second output signals has a half duty cycle when a duty cycle of the input signal or of the respective first and second output signals deviates from the half duty cycle.
In an embodiment, the first signal transfer path comprises first and second inverters that are serially coupled between the input signal and the first output signal, and the second signal transfer path comprises third, fourth, and fifth inverters that are serially coupled between the input signal and the second output signal.
In an embodiment, the duty cycle correction circuit charges or discharges a control node in response to the first and second output signals. Pull-up and pull-down speeds of the first inverter are adjusted according to a potential of the control node, and pull-up and pull-down speeds of the fourth inverter are adjusted according to an inverted potential of the control node.
In an embodiment, the duty cycle correction circuit adjusts the pull-up speed of the first inverter in an increasing direction, and adjusts the pull-down speed of the first inverter in a decreasing direction, when the potential of the control node is relatively decreased to a previous potential thereof. Further, the duty cycle correction circuit adjusts the pull-up speed of the fourth inverter in a decreasing direction and the pull-down speed of the fourth inverter in an increasing direction, when the inverted potential of the control node is relatively increased to a previous potential thereof.
In this embodiment, the first and fourth inverters each comprise a stack inverter having first pull-up and pull-down transistors controlled by the potential of the control node, and second pull-up and pull-down transistors controlled by an input signal of the corresponding inverter.
In this embodiment, when a potential of the control node is relatively decreased and the input signal transitions from a low level to a high level, a high-to-low transition of an output signal of the first inverter becomes relatively slower. When a potential of the control node is relatively decreased and the input signal transitions from the high level to the low level, a low-to-high transition of the output signal of the first inverter becomes relatively faster.
In this embodiment, when an inverted potential of the control node is relatively increased and an input signal of the fourth inverter transitions from a high level to a low level, a low-to-high transition of an output signal of the fourth inverter becomes relatively slower. When the inverted potential of the control node is relatively decreased and the input signal of the fourth inverter transitions from the low level to the high level, a high-to-low transition of the output signal of the fourth inverter becomes relatively faster.
In this embodiment, the duty cycle correction circuit comprises a pull-up transistor for pulling up the control node in response to the first output signal, a pull-down transistor for pulling down the control node in response to an inverted version of the second output signal, a feedback capacitor coupled between the control node and a ground voltage, and an inverting amplifier for inverting a potential of the control node to output the inverted potential of the control node.
According to another aspect of the invention, a phase splitter circuit includes a first
Callahan Timothy P.
Cox Cassandra
Samsung Electronics Co,. Ltd.
Volentine & Francos, PLLC
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