Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-06-30
2002-12-10
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C430S005000, C430S396000
Reexamination Certificate
active
06493866
ABSTRACT:
COPYRIGHT NOTICE
A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the patent and trademark office patent files or records, but otherwise reserves all copyright rights whatsoever.
Microfiche Appendix A, consisting of 1 sheets and 14 frames, is a part of the present disclosure and is incorporated herein by reference in its entirety. Microfiche Appendix A contains descriptions of commands to software tools.
BACKGROUND
In semiconductor manufacture, micro lithography is used in the formation of integrated circuits on a semiconductor wafer. During a lithographic process, a form of radiant energy, such as ultraviolet light, is passed through a photo mask or a reticle and onto the semiconductor wafer. “Light” is not limited to the visible spectrum. The photo mask contains opaque and transparent regions formed in a predetermined pattern. A grating pattern, for example, can be used to define parallel spaced conducting lines on a semiconductor wafer. The ultraviolet light exposes the mask pattern on a layer of resist formed on the wafer. The resist is then developed to remove either the exposed portions of resist for a positive resist or the unexposed portions of resist for a negative resist. The patterned resist can then be used for subsequent semiconductor fabrication processes such as ion implantation or etching.
As microcircuit densities have increased, the size of the features of semiconductor devices has decreased to the sub-micron level. These sub-micron features may include the width and spacing of metal conducting lines or the size of various geometric features of active semiconductor devices. The requirement of sub-micron features in semiconductor manufacture has necessitated the development of improved lithographic processes and systems. One such improved lithographic process is known as phase shift lithography.
Recently, different techniques have been developed in the art for fabricating different types of phase shifting photo masks. One type of phase shifting mask, named after a pioneer researcher in the field, M. D. Levenson, is known in the art as a “Levenson” or “strong” phase shifting mask. This type of mask is also referred to as an “alternating aperture” phase shifting mask because every other aperture contains a phase shifter. The term “strong” refers to the use of non-attenuated or full strength phase shifting illumination.
This type of mask is typically formed on a transparent quartz substrate. An opaque layer, formed of a material such as chromium, is deposited on the quartz substrate and etched with openings in a desired pattern. Phase shifting areas on the mask are formed by depositing a phase shifting material over the opaque layer and into every other opening in the opaque layer. The phase shifting areas may also be formed by etching a pocket or trench in the transparent substrate. The target features for phase shift lithography are the opaque regions. Each opaque target feature is bordered by a transparent, i.e. non phase shifting, opening on one side and a phase shifting opening on the other side. The transparent openings and the phase shifting openings are referred to as shifter polygons.
With phase shift lithography, the interference of light rays is used to improve the resolution and depth of focus of an image projected onto a target. In “strong” phase shift lithography, the phase of an exposure light at the object is controlled such that adjacent bright areas are formed preferably 180 degrees out of phase with one another. Dark regions are thus produced between the bright areas by destructive interference even when diffraction without phase shifting would otherwise cause these areas to be exposed away. This technique improves total resolution at the object and allows resolutions as fine as 0.1 &mgr;m or finer to occur.
In general, a strong phase shifting photo mask is constructed with a repetitive pattern having three distinct layers or areas. An opaque layer provides areas that allow no light transmission. A transparent layer provides areas which allow close to 100% of light to pass through. A phase shift layer provides areas which allow close to 100% of light to pass through but phase shifted 180 degrees from the light passing through the transparent areas. The transparent areas and phase shift areas are situated such that light rays diffracted are canceled out in a darkened area therebetween. This creates the pattern of dark and bright areas which can be used to clearly delineate features of a pattern defined by the opaque layer of the mask on a photopatterned semiconductor wafer.
In order to generate a phase shift lithography mask, target features in a given circuit design, or features that are small enough to require phase shift lithography, are identified. Next, shifter polygons meeting dimensional criteria dictated by mask-making constraints and optical performance are created on either side of each target feature. Then, the shifter polygons are “colored,” that is, assigned one of two color designations, so that each target feature is sandwiched between shifter polygons of opposing colors. The two colors correspond to the phase shifted and non phase shifted apertures.
An electronic representation of such a mask can be generated using a design rule check (DRC) tool of a layout verification software tool. Examples of such a layout verification tool include (1) HERCULES software available from Avant! Corporation, 46871 Bayside Parkway, Fremont, Calif. 94538, Tel 510.413.8000, (2) VAMPIRE software available from Cadence Design Systems, Inc, 555 River Oaks Parkway, San Jose, Calif. 95134, Tel 408.943.1234, and (3) CALIBRE software available from Mentor Graphics Corporation, 8005 SW Boeckman Road, Wilsonville, Oreg., 97070, Tel 503.685.7000.
The phase-shift mask is created in the DRC tool by applying several logical (such as not, and, or, and xor) and sizing operations to a representation of the circuit design to form output layers, such as a layer of target features, a layer of shifter polygons that pass light of phase 0°, and a layer of shifter polygons that pass light of phase 180°. The output layers correspond to features created on one or more masks. For simplicity, assigning shifter polygons to a particular output layer is referred to as assigning phase to a polygon or phase mapping a polygon.
In selective phase shift masks, target features are selected by applying a set of dimensional measurements to select only features with a specified width, i.e. smaller than the resolution of conventional optical lithography. The shifter polygons are created by applying sizing and logical operations using the input pattern as a starting point.
Once the shifter polygons are created, one needs to assign phases to the shifter polygons. Assigning phase by hand is burdensome particularly for random logic. Typical computer methods require first sorting the shifter polygons into runs of shifter polygons oriented in the same direction. A “run” refers to a horizontal “run” of shifter polygons separated by target features, such that the run unambiguously alters between a shifter polygon and a target feature. Phase is then assigned by traversing the run in the direction of the run and assigning phase to the shifter polygons by alternating between phase 0 and phase 180. If two shifter polygons are not separated by a target feature, they are not interrelated. Such methods are limited. They work for a run in which the target features extend in the same predetermined direction such that traversing all of the shifter polygons in the run requires moving in only one direction. Such methods also require the data to first be sorted into runs. Sorting therefore adds an extra data processing step. Furthermore, in complex configurations where the target features contain branches or loops, it may not be possible to map the pattern by this technique alone. Therefore, it is des
Garbowski Leigh Marie
Silicon Valley Patent & Group LLP
Smith Matthew
Suryadevara Omkar
Synopsys Inc.
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