Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
2008-10-15
2010-11-30
Fan, Chieh M (Department: 2611)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S355000, C327S307000
Reexamination Certificate
active
07844023
ABSTRACT:
A system for use with a multi-phase clock generator is disclosed. It should also be understood that the multiphase clock generator can be a phase lock loop (PLL), delay lock loop (DLL), or any other circuit capable of providing a multiphase clock. The system comprises at least two phase detectors coupled to the multi-phase clock generator for receiving component clock signals of the multi-phase clock generator, wherein at least some of the component clock signals are offset from each other in phase. Each of the phase detectors detects phase differences between pairs of component clock signals. The system includes a summer coupled to the at least two phase detectors for measuring the phase differences between the at least two phase detectors. The system includes at least one variable delay element for receiving the measured phase difference and for providing a delay which is proportional to an output value of the summer. The delay is used to reduce the phase differences.
REFERENCES:
patent: 5548251 (1996-08-01), Chou et al.
patent: 5663665 (1997-09-01), Wang et al.
patent: 6052011 (2000-04-01), Dasgupta
patent: 6100767 (2000-08-01), Sumi
patent: 6111445 (2000-08-01), Zerbe et al.
patent: 6275072 (2001-08-01), Dally et al.
patent: 6388482 (2002-05-01), Schnell et al.
patent: 6486716 (2002-11-01), Minami et al.
patent: 6978012 (2005-12-01), Casper
patent: 7065025 (2006-06-01), Kiyose
patent: 7136445 (2006-11-01), Houtman
patent: 7414445 (2008-08-01), Heyne
patent: 2001/0043649 (2001-11-01), Farjad-Rad
patent: 2002/0049936 (2002-04-01), Gutnik et al.
patent: 2002/0085656 (2002-07-01), Lee et al.
patent: 2002/0140512 (2002-10-01), Stockton
patent: 2003/0012321 (2003-01-01), Tokutome et al.
patent: 2003/0174003 (2003-09-01), Nogami
patent: 2007/0047689 (2007-03-01), Menolfi et al.
Non-Final Office Action for U.S. Appl. No. 10/764,003, filed Jan. 22, 2004 and mail date of Dec. 11, 2007 with Notice of References Cited. 14 pages.
Response to Office Action, U.S. Appl. No. 10/764,003, filed Jan. 22, 2004 mailed to the USPTO on Apr. 8, 2008. 13 pages.
Park et al., A 1.8 GHz Self-Calibrated Phase-Locked Loop with Precise I/Q Matching, IEEE Journal of Solid-State Circuits, vol. 36, No. 5, May 2001, pp. 777-783.
B. Razavi, Design Considerations for Direct-Conversion Receivers, IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 44, No. 6, Jun. 1997, pp. 428-435.
Yang et al., A 0.5-um CMOS 4.0 Gbit/s Serial Link Transceiver with Data Recovery Using Oversampling, IEEE Journal of Solid-State Circuits, vol. 33, No. 5, May 1998, pp. 713-718, 720-722.
Yu et al., A Novel Adaptive Mismatch Cancellation System for Quadrature IF Radio Receivers, IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 46, No. 6, Jun. 1999, pp. 789-795, 798-801.
Fan Chieh M
Fotakis Aristocratis
Rambus Inc.
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