Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1999-09-28
2003-12-09
Tran, Khai (Department: 2631)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
Reexamination Certificate
active
06661863
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to clock synchronization and, particularly, to an improved system and method for locking a signal onto a non-integer multiple of a reference frequency signal.
A phase locked loop (PLL) circuit generates a frequency which is an integer multiple of a reference frequency, usually a stable source such as a crystal oscillator. However, certain applications require a stable signal source which is a non-integer multiple of a stable reference source.
SUMMARY OF THE INVENTION
A phase mixer according to the present invention is provided which generates non-integer multiples of a stable reference source. Briefly, the phase mixer according to one embodiment includes a recirculating shift register and a multiplexer. The shift register output addresses the multiplexer, and the multiplexer in turn selects as the output one of the phases of the reference oscillator. The output of the multiplexer is used to clock the shift register. Because the reference oscillator phases are themselves shifted with reference to one another, sequential selection of the phase pulses as output pulses results in an output which is a non-integer multiple of the reference oscillator frequency.
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Copy of European Search Report for EP Appln. No. 00 106480.7; date search was completed: Jun. 23, 2000.
Fish & Richardson P.C.
Infineon Technologies North America Corp.
Tran Khai
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