Phase-locked loop with small phase error

Details Phase-locked loop with small phase error Phase-locked loop with small phase error

2000-02-18

2001-01-30

Ghebretinsae, Temesghen (Department: 2734)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C327S147000

Reexamination Certificate

active

06181758

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed to a phase-locked loop for controlling the phase of an output signal S
2
dependent on a reference signal S
1
.
2. Description of the Prior Art
FIG. 4
shows a block circuit diagram of a known, digital phase-locked loop (PLL) of the above type. By comparison in a phase detector
26
, the phase position of the output signal S
2
having the frequency f
2
is regulated to the phase of the reference signal S
1
having the frequency f
2
. The follow-up of the output signal S
2
, however, is not error-free. The phase timing error x(t), i.e. the phase difference between the reference signal S
1
and the output signal S
2
, is established in digital phase-locked loops by the cycle duration or quantization stage T
2
=1/f
2
of the output signal, which, as indicated in
FIG. 4
by arrow lines, is also employed as the clock frequency for the digital components such as the dividers
24
,
27
, the phase detector
26
of the integrator
28
and the digital-to-analog converter
30
.
The reason why a phase timing error arises in the phase-locked loop shown in
FIG. 4
is explained below on the basis of
FIGS. 5
,
6
A,
6
B and
6
C.
The phase positions of the signals S
2
, S
2
M (output signal at the input of the phase detector divided by M) and S
2
N (reference signal at the input of the phase detector divided by N) relative to the reference signal S
1
are shown at different, successive times t
0
(FIG.
6
A), t
1
(
FIG. 6B
) and t
2
(FIG.
6
C). A slighter higher eigenfrequency (leading phase position) of the crystal oscillator
31
is assumed. The (higher-frequency) signal S
2
samples the phase of the reference signal S
1
with a cycle T
2
=1/f
2
(symbolized in
FIGS. 6A through 6C
by a vertical arrow). When the phase shift of the signals S
1
and S
2
relative to one another exceeds the cycle duration T
2
, then this is acquired by the phase detector
26
and the voltage-controlled oscillator
31
is controlled with the integrator
28
, the summing circuit
29
and the digital-to-analog converter
30
, to correspondingly re-adjust the frequency of the signal, so that the phase shift between S
1
and S
2
is minimized. Within the cycle duration, however, the linking of the signals S
1
N, S
2
M and S
2
—which are synchronous relative to one another—to the reference signal S
1
is cancelled. This dead time fundamentally arises due to the sampling of the reference signal S
1
by the oscillator signal S
2
. Any drift of the oscillator
31
will not re-adjusted in this way during the dead time T
2
and thus fully affects the output signal S
2
. The phase difference is acquired by the phase detector
26
only given a phase timing error x=T
2
, and the frequency of the oscillator
31
is correspondingly readjusted. A time-dependent phase timing error x(t) having a maximum value &Dgr;x=T
2
thus occurs, the typical time curve thereof being shown in FIG.
5
. One can recognize a typical delta or sawtooth-shaped curve that is first defined in the leading direction by the drift of the oscillator. When the error x(t) reaches the threshold T
2
, a lower locking voltage that reduces the frequency of the oscillator
31
is generated. The error x(t) then in turn becomes smaller until the phase detector
26
no longer acquires a phase difference, and the locking voltage at the oscillator subsequently disappears.
FIG. 6B
shows the situation when a phase timing error 0≦x≦T
2
exists between the signal S
1
and the signals S
2
, S
1
N and S
1
M, which are synchronous relative to one another. When the phase timing error continues to increase until x=T
2
has been reached (FIG.
6
C), the sampling by the signal S
2
acquires the changed phase position, and the oscillator is correspondingly re-adjusted.
An optimally small phase timing error is advantageous for specific applications such as, for instance, clock editing circuits in synchronous digital communication networks.
It is known to reduce the phase timing error x(t) by employing high-frequency, re-adjusted, controllable oscillators and to thus achieve a high frequency of the signal S
2
. This method, however, has the disadvantage that the operating range of a voltage-controlled crystal oscillator (VCXO) decreases with the square of the harmonic of the crystal oscillator that is employed, i.e., the range of control of the oscillator frequency becomes smaller as the operating frequency of the crystal oscillator becomes higher relative to the fundamental oscillation thereof. For output signals of higher frequency S
2
, moreover, the digital components of the phase-locked loop must be realized with fast logic circuits, causing an increase in cost and power consumption. Due to the high number of synchronously clocked flip-flops in counters and dividers, the operating frequency is considerably lower than the limit frequency of, for example, a flip-flop. In one example with 500 synchronous flip-flops, an operating frequency of only 50 MHZ could be achieved with 0.5 &mgr;m CMOS technology, corresponding to a phase timing error of approximately 20 ns.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a phase-locked loop having only a small phase error. object is inventively achieved in a phase-locked loop having a sampling circuit for sampling the reference signal S
1
with the output signal S
2
and for generating a sampling signal S
1
A, a jitter modulation circuit for generating a sampling signal S
1
AJ delayed by a defined time duration and for alternating output of the undelayed sampling signal S
1
A and the delayed sampling signal S
1
AJ, a phase detector for acquiring an average phase difference between the output signal S
2
and the delayed and undelayed sampling signals S
1
A and S
1
AJ, and a controllable oscillator for generating the output signal S
2
having a frequency that is controllable dependent on the average phase difference acquired by the phase detector. Due to the averaging, phase shifts between the reference signal S
1
and the output signal S
2
that lie within a sampling period of the Signal S
2
can be “noticed” by the phase detector. The phase timing error thus can be significantly reduced.
The jitter modulation circuit preferably has a delay circuit such as, for example, a D flip-flop for generating the delayed reference signal S
1
AJ and a switching stage for alternating delivery of the delayed signal S
1
AJ and the undelayed signal S
1
A to the phase detector. The switching stage preferably is a digital multiplexer.
The signal delay generated by the delay circuit preferably corresponds to a cycle duration T
2
of the output signal S
2
.
The switching frequency of the switching stage is selected high in relationship to the transfer function of the phase-locked loop, so that the switch signal of the switching stage is largely suppressed in the output signal, so that no disturbances caused by the jitter modulation appear in the output signal.
The inventive phase-locked loop can have a first frequency divider for frequency-division of the reference signal S
1
by N before delivery to the phase detector and a second frequency divider for frequency-division of the output signal S
2
by M before delivery to the phase detector. Signals S
1
, S
2
of different frequencies thus can be brought into a fixed phase relationship with the phase-locked loop.
The switching cycle of the switching stage preferably amounts to 2N times the clock period t
2
of the output signal S
2
.
In order to facilitate a symmetrical phase fine-control, the pulse-duty factor of the undelayed signal S
1
A generated by the switching stage and the pulse-duty factor of the delayed signal S
1
AJ preferably are 1:1.
The inventive circuit is preferably realized with purely digital components, thereby achieving a dependable fine phase control is enabled with a low number of gates.


REFERENCES:
patent: 5056116 (1991-10-01), Shimada et al.
patent: 5373255 (1994-12-01), Bray et al.
patent: 5828255 (1998-10-01), Kelkar et

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