Phase locked loop with reduced phase noise

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

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375376, 327336, 331 16, 331 17, 331 25, 455260, H04L 700

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055175341

ABSTRACT:
An accumulator-based phase locked loop reduces phase noise by shifting the energy of the phase noise to higher frequencies. A second accumulator is inserted between a first accumulator and a pulse generator to integrate a phase error from the first accumulator referenced to a clock signal. The output of the pulse generator is an approximation frequency signal that is compared with a comparable frequency signal derived from a reference signal to produce an error signal to control the frequency of the clock signal.

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Microwaves & RF--"Fast Synthesizers"--p. 122--Sep. 1991.
Hewlett-Packard Journal Feb. 1989--"A Generating a Phase-Locked Binary Reference Frequency"--p. 68.
Analog Devices, Inc.--Mixed-Signal Design Seminar, VI-4 through VI-7 Copyright @ 1991, ISBN-0-916550-08-7.

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