Phase-locked loop with protected output during instances when th

Details Phase-locked loop with protected output during instances when th Phase-locked loop with protected output during instances when th

1997-10-16

1999-12-21

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

331DIG2, 327159, H03D 324

Patent

active

060059044

ABSTRACT:
A circuit is provided for controlling or regulating a phase-locked loop (PLL) output during times when the PLL is unlocked. Noise or corruption on the input signal of the PLL may cause the PLL output frequency to suddenly rise to match the input signal frequency. In many instances, the noise or corruption cannot be filtered by the low pass filter within the PLL. A detection circuit is coupled to receive the input signal, and discern times in which non-filterable noise occurs. The detection circuit may include a decoder which decodes, e.g., error correction coding within the input signal data stream to indicate possible instances in which the PLL will unlock. Once the detection circuit indicates an unlock condition and forwards an unlock selection signal to a multiplexer, the multiplexer chooses a frequency divided clocking signal rather than the PLL output clocking signal. The frequency divided clocking signal transitions at a rate acceptable to a digital processor, while the PLL output clocking signal during an unlock state is not acceptable. Thus, the digital processor can maintain its operating state during times when the PLL clocking signal exceeds the processor maximum operation frequency.

REFERENCES:
patent: 4534044 (1985-08-01), Funke et al.
patent: 4849998 (1989-07-01), Poklemba
patent: 5123030 (1992-06-01), Kazawa et al.
patent: 5184350 (1993-02-01), Dara
patent: 5406590 (1995-04-01), Miller et al.
patent: 5579353 (1996-11-01), Parmenter et al.
patent: 5633855 (1997-05-01), Naito
patent: 5663687 (1997-09-01), Kozu
patent: 5838749 (1998-11-01), Casper et al.
English Abstract for Patent Abstract of Japan; Publication No. 06268518; Publication Date Sep. 22, 1994; Application Date Mar. 9, 1993; Application No. 05076179; Applicant Sony Corp.
International Search Report for PCT/US 98/21512 mailed on Feb. 12, 1999.

Affiliated with

Also associated with

Rating

Phase-locked loop with protected output during instances when th does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Phase-locked loop with protected output during instances when th, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Phase-locked loop with protected output during instances when th will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-512621