Phase locked loop with improved lock time and stability

Details Phase locked loop with improved lock time and stability Phase locked loop with improved lock time and stability

1997-01-07

1999-03-30

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

331 25, 327156, H03D 324, H03L 700

Patent

active

058898298

ABSTRACT:
A phase-locked loop (PLL) circuit is used to synchronize a local clock frequency with an edge of a reference clock frequency, employing a phase detector to compare the local clock frequency and the reference clock frequency to generate a control signal indicative of the need to increase or to decrease the local clock frequency for phase locking thereof to the reference clock frequency. A voltage controlled oscillator (VCO) is responsive to a signal voltage derived from the control signal to vary the local clock frequency as necessary to achieve phase locking. A loop filter has a reference voltage threshold level which is pre-programmable to enable the loop filter to respond to the control signal by adjusting the signal voltage as a virtual step function toward the programmed reference voltage threshold level before application to the VCO, and then cycling up and down in a search for a stable control signal voltage to reduce the time necessary to achieve the desired phase locking.

REFERENCES:
patent: 4270093 (1981-05-01), Miille
patent: 5546053 (1996-08-01), Ichimaru
patent: 5577086 (1996-11-01), Fujimoto et al.
patent: 5656975 (1997-08-01), Imura
patent: 5675291 (1997-10-01), Sudjian

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