Phase locked loop with adaptive loop bandwidth

Details Phase locked loop with adaptive loop bandwidth Phase locked loop with adaptive loop bandwidth

2006-11-14

2006-11-14

Nguyen, Linh My (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S157000

Reexamination Certificate

active

07135900

ABSTRACT:
A semiconductor device that includes an adaptive phase locked loop with improved loop stability and a faster locking rate. In one embodiment, this is accomplished in a manner that does not require an additional second charge pump for loop stability, and therefore the resulting phase locked loop of the present invention consumes less chip die area. In another embodiment, multiple charge pumps are used and the resulting response time for locking is improved over that which can be achieved by conventional embodiments.

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Sidiropoulos, Stefanos, et al., “Adaptive Bandwidth DLLs and PLLs using Regulated Suuply CMOS Buffers,” Rambus Inc and Stanford University, 2000 Symposium on VLSI Circuits Digest of Technical Papers, pp. 124-7.

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