Phase locked-loop using sub-sampling

Details Phase locked-loop using sub-sampling Phase locked-loop using sub-sampling

2000-05-25

2002-10-08

Ghebretinsae, Temesghen (Department: 2631)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C327S157000

Reexamination Certificate

active

06463112

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is in the field of phase locked-loop (PLL)-based frequency synthesizers. More specifically, the present invention provides a PLL-based frequency synthesizer with a sub-sampling feedback loop that is particularly well-suited for use in a wireless device.
2. Description of the Related Art
The frequency synthesizer is an important element in any wireless device. It is responsible for generating a sinusoidal output signal with an accurate frequency that is used to translate the frequency band of the information channels transmitted by the wireless device. By tuning the frequency synthesizer, channel selection among the information channels is achieved. The spectral purity of the frequency synthesizer's output signal has an effect on the information signal selected, which is typically converted down to baseband or to an intermediate frequency. The spectral purity of this output signal is characterized by the amount of spurious signals and the amount of phase-noise.
FIG. 1A
sets forth a prior art PLL-based frequency synthesizer utilizing a voltage-controlled oscillator (VCO)
12
configured in a feedback loop. In this circuit, the frequency output of the VCO (f
0
), which is the output signal from the frequency synthesizer, is divided down to a low frequency using a 1/N divider circuit
14
, and then fed back to the VCO
12
input through circuits
16
,
18
. The divider
14
output signal is coupled to one input of a phase-frequency detector (PFD)
16
. A fixed reference frequency, f
ref
, is coupled to the other input of the PFD
16
. The output of the PFD
16
is coupled to and filtered in a loop filter
18
, which sets the bandwidth and spurious rejection of the circuit. The output of the filter
18
is then coupled to the input of the VCO
12
.
In the PLL shown in
FIG. 1A
, the reference frequency (f
ref
) is fixed and is derived from a crystal oscillator (not shown). Tuning in this prior art circuit is achieved by changing the division ratio N. Since N is an integer, the tuning step will be equal to f
ref
. Hence, f
ref
must be chosen to be equal to the desired channel spacing according to whatever wireless standard is associated with the wireless device. Due to spurious rejection considerations, the loop bandwidth (BW) is typically limited to approximately f
ref
/10. Having such a small bandwidth, this prior art circuit generally does not inhibit the VCO's phase-noise over the frequency range of interest. It is only by increasing the power of the VCO
12
, and/or using an off-chip VCO, that the desired phase-noise performance can be attained in this prior art scheme.
A major source of phase-noise in such a PLL
10
is the VCO
12
. The phase-noise of a free-running VCO is generally inversely proportional to its power consumption and drops quadratically with the offset from the circuit's center frequency. When configured in a PLL, the phase-noise of the VCO is inhibited within the bandwidth (BW) of the PLL. This is due to the fact that, within it's BW, the PLL corrects for any jitter occurring in the VCO. Thus, in order to reduce the phase-noise caused by the VCO, it is desired to increase its BW. However, this is in conflict with the other objective of maintaining adequate spurious rejection.
The spurious tone in a PLL arises from the input reference frequency. This is due to the fact that the PFD
16
in
FIG. 1A
produces pulses every cycle of the input clock. Unless the loop bandwidth is small enough to reject it, this frequency will appear at the output of the PLL as discrete tones, at an offset from the carrier equal to f
ref
. Hence, the bandwidth of the PLL is usually a decade less than the reference frequency.
The known architecture in
FIG. 1A
also has problems because of the division ratio, N. This is so because when the phase-noise in the reference signal is mapped to the output, it is multiplied by a factor of N
2
(or, equivalently, increased by 20 log(N) dB). Since N is usually very large (e.g., 5,000-70,000) in such PLLs, even a relatively “clean” input signal may contaminate the output spectrum.
A traditional alternative to the PLL of
FIG. 1A
is a fractional-N architecture, which relies on periodically hopping the division ratio (N) between two consecutive integers such that the average resulting division ratio is a fraction. While this results in a moderate reduction of the division ratio (e.g., factor of 8 or 16), a spur at the channel spacing still persists, necessitating a low BW.
FIG. 1B
sets forth another prior art circuit architecture
10
′ for a phase-locked loop using a VCO. Similar to the first prior art circuit of
FIG. 1A
, in
FIG. 1B
a VCO
12
′ is configured in a feedback loop. The output of the VCO (f
0
) is first divided down to an intermediate frequency using a 1/N divider circuit
14
′, where N is an integer. The divider
14
′ outputs a signal that is input to a PFD
16
′. A reference frequency, f
ref
′ is also input to the PFD
16
′. The output from the PFD
16
′ is fed to and filtered in a loop filter
18
′ , which sets the bandwidth and spurious rejection of the circuit. The filter
18
′ then outputs a signal to the VCO
12
′. In this second prior art circuit, however, the reference frequency (f
ref
′) is not fixed as in
FIG. 1A
, but is a tunable frequency that is derived from a digital frequency synthesizer (DDS)
20
′, or some other type of frequency synthesizer. Using this architecture, the reference frequency (f
ref
′) can be made much larger than the channel spacing and the BW proportionally increased.
This architecture, however, suffers from several problems. The primary problem relates to the selection of the division ratio N. If the division ratio N is small, then the DDS
20
′ will have to operate at a relatively high frequency, which leads to excessive power consumption in the circuit. This high frequency operation also leads to greater difficulty in designing the digital-to-analog convertor (DAC) at the DDS output. If the division ratio N is large, then the phase-noise of the DDS
20
′ will start to dominate since it is multiplied by N
2
when mapped to the output. Thus, the problem of phase-noise found in the prior art system in
FIG. 1A
is transferred in this second prior art system shown in
FIG. 1B
from the VCO
12
to the DDS
20
.
One solution to this problem is to use some form of dual-loop architectures where the VCO signal is mixed with the output of another PLL, thus converting down the VCO signal to a low frequency while keeping the division ratio small. However, this requires the use of a mixer operating at a high RF frequency and the use of two PLLs, which leads to high power consumption. Also, the output of the second PLL must be “clean” since it will affect the phase-noise in the frequency synthesizer output.
SUMMARY OF THE INVENTION
A PLL-based frequency synthesizer is provided that includes a phase detector, a loop filter, a VCO, a sampler and filter system, and a frequency divider. This architecture reduces the high division ratio (N) necessary in a classical PLL-based frequency, thus reducing the PLL phase-noise, without adding any extra loops or VCOs. This is achieved through sub-sampling the VCO output signal in the feedback path. The sampler is placed in the feedback loop following the VCO and is clocked at a low frequency (sub-sampling). The output of the sampler is the beat frequency between the VCO frequency and the sampling clock (in addition to harmonics that are filtered-out by a low-pass filter (LPF)). The LPF in the feedback loop attenuates any spurious tones resulting from the sampling operation. A frequency divider is then used to bring down the feedback signal to the frequency of the phase detector input. Since the feedback signal has already been reduced in frequency by the sampling operation, the division ratio (N) in this frequency divider is greatly reduced when compared to the classical PL

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