Phase-locked loop using multi-phase feedback signals

Details Phase-locked loop using multi-phase feedback signals Phase-locked loop using multi-phase feedback signals

2005-04-27

2009-02-24

Phu, Phuong (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S373000, C375S374000, C375S375000, C327S156000, C327S158000

Reexamination Certificate

active

07496168

ABSTRACT:
A signal generator, such as a fractional-N PLL, has, in its feedback signal path, a divider, a phase circuit, and a fractional accumulator that generates control signals for the divider and the phase circuit. The divider control signal controls the divisor value applied by the divider. In one embodiment, a phase selector selects, based on the phase-circuit control signal, one of a plurality of phase-shifted output signals generated by the PLL's main signal path (e.g., by a multi-phase VCO) and the divider generates the feedback signal for the PLL from the selected signal. In another embodiment, the divider generates a divided signal from one of the phase-shifted output signals, and a phase mixer generates, from the divided signal, a plurality of phase-shifted divided signals and selects, based on the phase-circuit signal, one of the phase-shifted divided signals as the PLL's feedback signal.

REFERENCES:
patent: 6424192 (2002-07-01), Lee et al.
patent: 7283002 (2007-10-01), Puma et al.
“A 1.8-Ghz Self-Calibrated Phase-Locked-Loop with Precise I/Q Matching,” by Chan-Hong Park et al., IEEE Journal of Solid-State Circuits, vol. 36, No. 5, May 2001, pp. 777-783.
“Fractional/Integer-N PLL Basics,” Texas Instruments, Technical Brief SWRA029, Aug. 1999, pp. 31-40.

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